I/O端口地址表

I/O端口地址表

Port addresses are not always constant across PC, AT and PS2

Unless marked, port addresses are relative to PC and XT only

 

000-00F 8237 DMA controller:

 

000 Channel 0 address register

001 Channel 0 word count

002 Channel 1 address register

003 Channel 1 word count

004 Channel 2 address register

005 Channel 2 word count

006 Channel 3 address register

007 Channel 3 word count

008 Status/command register

009 Request register

00A Mask register

00B Mode register

00C Clear MSB/LSB flip flop

00D Master clear temp register

00E Clear mask register

00F Multiple mask register

 

 

010-01F 8237 DMA Controller (PS2 model 60 & 80), reserved (AT)

 

020-02F 8259A Master Programmable Interrupt Controller:

 

020 8259 Command port (see 8259)

021 8259 Interrupt mask register (see 8259)

 

030-03F 8259A Slave Programmable Interrupt Controller (AT,PS2)

 

040-05F 8253 or 8254 Programmable Interval Timer:

 

040 8253 channel 0, counter divisor

041 8253 channel 1, RAM refresh counter

042 8253 channel 2, Cassette and speaker functions

043 8253 mode control (see 8253)

044 8254 PS/2 extended timer

047 8254 Channel 3 control byte

 

060-067 8255 Programmalbe Peripheral Interface (PC,XT,PCjr):

 

060 8255 Port A keyboard input/output buffer (output PCjr)

061 8255 Port B output

062 8255 Port C input

063 8255 Command/Mode control register

 

060-06f 8042 Keyboard Controller (AT,PS2):

 

060 8042 Keyboard input/output buffer register

061 8042 system control port (for compatability with 8255)

064 8042 Keyboard command/status register

 

070 CMOS RAM/RTC, also NMI enable/disable (AT,PS2, see RTC)

071 CMOS RAM data (AT,PS2)

 

080 Manufacturer checkpoint port

080-090 DMA Page Registers:

 

081 High order 4 bits of DMA channel 2 address

082 High order 4 bits of DMA channel 3 address

083 High order 4 bits of DMA channel 1 address

 

090-097 POS/Programmable Option Select (PS2):

 

090 Central arbitration control Port

091 Card selection feedback

092 System control and status register

094 System board enable/setup register

095 Reserved

096 Adapter enable/setup register

097 Reserved

 

0A0 NMI Mask Register (PC,XT) (write 80h to enable NMI, 00h disable)

0A0-0BF Second 8259 Programmalbe Interrupt Controller (AT,PS2):

 

0A0 Second 8259 Command port (see 8259)

0A1 Second 8259 Interrupt mask register (see 8259)

 

0C0 TI SN76496 Programmable Tone/Noise Generator (PCjr)

0C0-0DF 8237 DMA Controller 2 (AT):

 

0C2 DMA channel 3 selector (see ports 6 & 82)

 

0E0-0EF Reserved

 

0F0-0FF Math Coprocessor (AT,PS2)

0F0-0F5 PCjr Disk Controller:

 

0F0 Disk Controller

0F2 Disk Controller control port

0F4 Disk Controller status register

0F5 Disk Controller data port

 

0F8-0FF Reserved for future microprocessor extensions

 

100-10F POS Programmable Option Select (PS2):

 

100 POS Register 0, Adapter ID byte (LSB)

101 POS Register 1, Adapter ID byte (MSB)

102 POS Register 2, Option select data byte 1

        Bit 0 is card enable (CDEN)

103 POS Register 3, Option select data byte 2

104 POS Register 4, Option select data byte 3

105 POS Register 5, Option select data byte 4

        Bit 7 is (-CHCK)

        Bit 6 is reserved

106 POS Register 6, subaddress extension (LSB)

107 POS Register 7, subaddress extension (MSB)

 

110-1EF System I/O channel

 

170-17F Fixed disk 1 (AT):

 

170 disk 1 data

171 disk 1 error

172 disk 1 sector count

173 disk 1 sector number

174 disk 1 cylinder low

175 disk 1 cylinder high

176 disk 1 drive/head

177 disk 1 status

 

1F0-1FF Fixed disk 0 (AT):

 

1F0 disk 0 data

1F1 disk 0 error

1F2 disk 0 sector count

1F3 disk 0 sector number

1F4 disk 0 cylinder low

1F5 disk 0 cylinder high

1F6 disk 0 drive/head

1F7 disk 0 status

 

200-20F Game Adapter

 

210-217 Expansion Card Ports (XT):

 

210 Write: latch expansion bus data

    read: verify expansion bus data

211 Write: clear wait,test latch

    Read: MSB of data address

212 Read: LSB of data address

213 Write: 0=enable, 1=/disable expansion unit

214-215 Receiver Card Ports

214 write: latch data, read: data

215 read: MSB of address, next read: LSB of address

 

21F Reserved

 

220-26F Reserved for I/O channel

 

270-27F Third parallel port (see PARALLEL PORT):

 

278 data port

279 status port

27A control port

 

280-2AF Reserved for I/O channel

 

2A2-2A3 MSM58321RS clock