whzxcvbnm的博客

10进制计数器VHDL代码 Library IEEE; Use IEEE.STD_LOGIC_1164.ALL; Use IEEE.STD_LOGIC_UNSIGNED.ALL; entity counter_10 is Port( reset : in std_logic; clock : in std_logic; num_out : out std_logic_vector(3 downto 0) ); end counter_10; architecture Behavior of counter_10 is signal temp: std_logic_vector(3 downto 0); begin num_out <= inner_reg; process(clock,reset)

用VHDL编写的交织器代码，ram通过调用ip核实现，并且有testbench 部分代码： waddress_gen: process(wclk) begin if(wclk'event and wclk='1')then if(wenable='1')then if(startflg='0')then waddress<="000000"; startflg<='1'; elsif(waddress<"111111")then waddress<=waddress+"000001"; else waddress<="111111"; end if; end if; end if; end process;

用VHDL编写的pn9序列生成器 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity pn_9 is port(clk,rst:in std_logic; pnout:out std_logic ); end pn_9; architecture behavior of pn_9 is signal shifter :std_logic_vector(8 downto 0); begin pnout<=shifter(8); process(rst,clk)

使用多线程和阻塞队列实现了ABC字母按顺序轮流打印

public static void quicksort(int[] array,int start, int end){ if(start>=end) return; int middle=partition(array,start,end); quicksort(array,start,middle-1); quicksort(array,middle+1,end); }