Embedded-DisplayPort (eDP) Output
2-lane/4-lane eDP @ 1.62/2.7Gbps per lane
FHD to WQXGA (2560*1600) supported
Up to 6dB pre-emphasis
18/24bit RGB Interface
Pixel clock up to 270MHz
Pin order reversal supported
Dual-channel 6/8bit LVDS (Sync) interface
400Mbps to 1Gbps per data pair
Channel and polarity swap supported
Any freq. between 19MHz and 100MHz
Crystal or single-ended clock input
Built-in 5000ppm SSC generator
I2C/SPI for chip configuration
Built-in eDP handshake protocol
2C-AUX channel for TCON/DPCD/EDID control
Built-in video test pattern
1.2V core supply
2.5V or 3.3V IO supply
RGB IO can go down to 1.8V
Power consumption ~ 70mW
@ 2048*1536*24bit*60Hz, LVDS mode
Deep-sleep mode power <1mW
QFN-56 (7mm x 7mm) package
2 Block Diagram
3 General Description
NCS8801 is an ultra-low-power RGB/LVDS-to-DisplayPort/eDP converter, which is designed for mobile devices including smartphones, tablets, laptops, etc. to support high-definition DP/eDP displays.
NCS8801 supports 4-lane DP/eDP output which is typically required to support QXGA (2048*1536) and above at 60Hz frame rate.
Thanks to the various proprietary circuit design techniques used in the chip, NCS8801 consumes only 70mW when operating at 2048*1536, 24bit, 60Hz, LVDS input, 4-lane eDP output mode. Mobile devices appreciate this low power consumption.
All the functions including both RGB and LVDS interfaces pack into a small 7mm*7mm QFN56 package which saves the precious space in mobile devices.
4 Pin Diagram
5.1 Pin Description (LVDS+I2C Mode)
5.2 Pin Description (RGB+I2C Mode)
6 Electrical Specifications
7 Register Table
8.1 Typical Application Schematics
8.2 PCB Layout Rules
a. Due to the high data rate of the eDP signal, characteristic impedance throughout the signal path needs to be well controlled. It is highly suggested to control the differential characteristic impedance of the PCB trace to be within 100ohm±10%. Low speed connectors are highly suggested to be avoided in the eDP signal path, especially in the 2.7Gbps mode.
b. The requirement on the LVDS side is less stringent but impedance discontinuities including Y-branching are highly suggested to be minimized.
c. The crosstalk and length of the RGB traces needs to be minimized.
d. The intra-pair mismatch in all differential pairs needs to be avoided.
e. eDP inter-lane skew is suggested to be controlled under 50mil.
f. LVDS inter-lane skew is suggested to be controlled under 100mil.
g. RGB inter-line skew is suggested to be controlled under 300mil.
8.3 Power-on Sequence
8.4 Typical Initialization Procedure
(I2C device ID of the chip is 0x70, write to address 0xE0, read from address 0xE1).
a. Configure register 0x09 to 01, to enter no video mode.
b. Configure register 0x4B, to choose between RGB and LVDS modes.
c. Configure register 0x0C, to choose between RGB and LVDS modes.
d. Configure registers 0x10-0x1F according to the display timing.
e. Configure register 0x35 to 41 if the lane rate is 2.7Gbps.
f. Configure register 0x30 to B0 if the lane rate is 2.7Gbps.
g. Configure register 0x30 to B1 if the lane rate is 2.7Gbps.
h. Configure register 0x00 according to the display mode, with bit 3 set to 1.
i. Configure register 0x09 to 00, to exit no video mode.
NCS8801 is packaged in 7mm*7mm 56-pin QFN, QFN56L (0707*0.75-0.40). The package dimensions are shown below. (Unit: mm)
10 Revision History
This document contains information on a new product. Specifications and information herein are subject to change without notice.