[power]一 Idle management

Many ARM systems are mobile devices and powered by batteries. In such systems, optimization of power use, and total energy use, is a key design constraint. Programmers often spend significant amounts of time trying to save battery life in such systems.

Power-saving can also be of concern even in systems that do not use batteries. For example, you might want to minimize energy use for reduction of electricity costs to the consumer, for environmental reasons, or to minimize the heat that the device generates.

Built into ARM cores are many hardware design methods aimed at reducing power use.

Energy use can be divided into two components:

• static power：Static power consumption, also often called leakage, occurs whenever the core
  logic or RAM blocks have power applied to them. In general terms, the leakage
  currents are proportional to the total silicon area, meaning that the bigger the chip, the higher the leakage. The proportion of power consumption from leakage gets significantly higher as you move to smaller fabrication geometries.
• dynamic power：Dynamic power consumption occurs because of transistor switching and is a
  function of the core clock speed and the numbers of transistors that change state
  per cycle. Clearly, higher clock speeds and more complex cores consume more
  power.

所以对于power的计算存在静态功耗和动态功耗的差异。整体的系统功耗包括静态功耗和动态功耗。通过上面的理解如下：

1. 静态功耗是由于core logic/RAM blocks还供着点导致的，比如说在系统suspend的时候，基本耗电就是静态功耗了。以CPU core为例子，当CPU运行在不同的频率点的时候，其本身带来的静态功耗也是随着CPU频率变大而变大的，但是没有CPU频率升高带来的动态功耗增加的快和大
2. 动态功耗一般是core 时钟频率变化和晶体管状态发生了变化导致的。比如我们常说CPU频率很高，功耗也很高，很多时候就是特指其动态功耗很高。当前在kernel5.4 EAS中只计算了动态功耗。

Power management-aware operating systems dynamically change the power states of cores, balancing the available compute capacity to the current workload, while attempting to use the minimum amount of power. Some of these techniques dynamically switch cores on and off, or place them into quiescent states, where they no longer perform computation. This means that they consume very little power. The main examples of these techniques are:

1. Idle management
2. Dynamic voltage and frequency scaling

功耗敏感的操作系统会随着系统的workload而改变core的电源状态，目的以最小的电源消耗满足其性能需求。DVFS相关的已经简单概述过了。所以只分析idle management内容：

When a core is idle, the Operating System Power Management (OSPM) transitions it into a low-power state. Typically, a choice of states is available, with different entry and exit latencies, and different levels of power consumption, associated with each state. The state that is used typically depends on how quickly the core is required again. The power states that can be used at any one time might also depend on the activity of other components in an SoC, beside the cores. Each state is defined by the set of components that are clock-gated or power-gated when the state is entered.

The time required to move from a low-power state to a running state, known as the wakeup latency, is longer in deeper states. Although idle power management is driven by thread behavior on a core, the OSPM can place the platform into states that affect many other components beyond the core itself. If the last core in a cluster becomes idle, the OSPM can target power states that affect the whole cluster. Equally, if the last core in an SoC becomes idle, the OSPM can target power states that affect the whole SoC. The choice is also driven by the use of other components in the system. A typical example is placing memory in self-refresh when all cores, and any other bus masters, are idle.

The OSPM has to provide the necessary power management software infrastructure to determine the correct choice of state. In idle management, when a core or cluster has been placed into a low-power state, it can be reactivated at any time by a core wakeup event. That is, an event that can wake up a core from a low-power state, such as an interrupt. No explicit command is required by the OSPM to bring the core or cluster back into operation. The OSPM considers the affected core or cores to be available at all times even if they are currently in a low-power state.
上面的意思大致如下：

1. Idle management有几种可选的power状态进入和退出，每种power state的进入和退出时延都是不相同的。都会对性能有影响。Power state越深，即save power越多，时延越大。
2. 对于CPU来说，每个core的单独管理自己的power state，当所有的core变为idle的话，那么这个cluster都会变成idle state。最终影响整个SoC。也就是说，系统的省电多少都是一个level一个level层层推进的。最终达到最省电level。
3. 那么如何才能进入到不同的省电level呢？需要power management software来来检测系统行为进入决策进入哪个power state。

Power and clocking

One way that can reduce energy use is to remove power, which removes both dynamic and static currents (sometimes called power-gating), or to stop the clock of the core which removes dynamic power consumption only and can be referred to as clock-gating.
ARM cores typically support several levels of power management, as follows:

1. Standby
2. Retention
3. Power down
4. Dormant mode
5. Hotplug

For certain operations, there is a requirement to save and restore the state before and after removing power. Both the time taken to do the save and restore, and the power consumed by this extra work can be an important factor in software selection of the appropriate power management activity.
对于某些power state，需要保存进入这个level的系统状态，当退出这个level时候，就需要恢复当时的系统状态。

The SoC device that includes the core can have additional low-power states, with names such as STOP and Deep sleep. These refer to the ability for the hardware Phase Locked Loop (PLL) and voltage regulators to be controlled by power management software.

Standby

In the standby mode of operation, the core is left powered-up, but most of its clocks are stopped, or clock-gated. This means that almost all parts of the core are in a static state and the only power drawn is because of leakage currents and the clocking of the small amount of logic that looks out for the wake-up condition.

This mode is entered using either the WFI (Wait For Interrupt) or WFE (Wait For Event) instructions. ARM recommends the use of a Data Synchronization Barrier (DSB) instruction before WFI or WFE, to ensure that pending memory transactions complete before changing state.

If a debug channel is active, it remains active. The core stops execution until a wakeup event is detected. The wakeup condition is dependent on the entry instruction. For WFI, an interrupt or external debug request wakes the core. For WFE, a number of specified events exist, including another core in the cluster executing the SEV instruction.

A request from the Snoop Control Unit (SCU) can also wake up the clock for a cache coherency operation in a multi-core system. This means that the cache of a core that is in standby state continues to be coherent with caches of other cores (but the core in standby does not necessarily execute the next instruction). A core reset always forces the core to exit from the standby condition.

Various forms of dynamic clock gating can also be implemented in hardware. For example, the SCU, GIC, timers, instruction pipeline or NEON blocks can be automatically clock gated when an idle condition is detected, to save power.

Standby mode can be entered and exited quickly (typically in two-clock-cycles). It therefore has an almost negligible effect on the latency and responsiveness of the core.

To an OSPM, a standby state is mostly indistinguishable from a retention state. The difference is evident to an external debugger and in hardware implementation, but not evident to the idle management subsystem of an operating system.

Retention

The core state, including the debug settings, is preserved in low-power structures, enabling the core to be at least partially turned off. Changing from low-power retention to running operation does not require a reset of the core. The saved core state is restored on changing from low-power retention state to running operation. From an operating system point of view, there is no difference between a retention state and standby state, other than method of entry, latency and use-related constraints. However, from an external debugger point of view, the states differ as External Debug Request debug events stay pending and debug registers in the core power domain cannot be accessed.

Standby和retention power state，几乎没有什么不同，不同点进入和退出的条件不同。但是它们的退出时延几乎可以忽略，对性能的影响很小很小。

Power down

In this state, the core is powered off. Software on the device must save all core state, so that it can be preserved over the power-down. Changing from power-down to running operation must
include:

1. A reset of the core, after the power level has been restored.
2. Restoring the saved core state.

The defining characteristic of power down states is that they are destructive of context. This affects all the components that are switched off in a given state, including the core, and in deeper states other components of the system such as the GIC or platform-specific IP. Depending on how debug and trace power domains are organized, one or both of debug and trace context might be lost in some power-down states. Mechanisms must be provided to enable the operating system to perform the relevant context saving and restoring for each given state. Resumption of execution starts at the reset vector, and after this each OS must restore its context.

Dormant mode

Dormant mode is an implementation of a power-down state. In dormant mode, the core logic is powered down, but the cache RAMs are left powered up. Often the RAMs are held in a low-power retention state where they hold their contents but are not otherwise functional. This provides a far faster restart than complete shutdown, as live data and code persists in the caches. Again, in a multi-core system, individual cores can be placed in dormant mode.

In a multi-core system that permits individual cores within the cluster to go into dormant mode, there is no scope for maintaining coherency while the core has its power removed. Such cores must therefore first isolate themselves from the coherence domain. They clean all dirty data before doing this and are typically woken up using another core signaling the external logic to re-apply power.

The woken core must then restore the original core state before rejoining the coherency domain. Because the memory state might have changed while the core was in dormant mode, it might have to invalidate the caches anyway. Dormant mode is therefore much more likely to be useful in a single core environment rather than in a cluster. This is because of the additional expense of leaving and rejoining the coherency domain. In a cluster, dormant mode is typically likely to be used only by the last core when the other cores have already been shut down.
Dormant mode是power down状态的另一种实现，在这个模式，core logic被下电，但是cache RAM还处于上电状态。并且其使用场合也是不相同的，如果core处于dormant mode，需要其他处于active core恢复dormant mode的core，会导致额外昂贵的离开/重新加入coherency domain的时延。所以使用场合是当某个cluster只剩下一个core，其他core都处于power down状态，则可以考虑进入dormant mode。

Hotplug

CPU hotplug is a technique that can dynamically switch cores on or off. Hotplug can be used by the OSPM to change available compute capacity based on current compute requirements. Hotplug is also sometimes used for reliability reasons. There are a number of differences between hotplug and use of a power-down state for idle:

1. When a core is hot unplugged, the supervisory software stops all use of that core in interrupt and thread processing. The core is no longer considered to be available by the calling OS.
2. The OSPM has to issue an explicit command to bring a core back online, that is, hotplug a core. The appropriate supervisory software only starts scheduling on or enabling interrupts to that core after this command.

Operating systems typically perform much of the kernel boot process on one primary core, bringing secondary cores online at a later stage. Secondary boot behaves very similarly to hotplugging a core into the system. The operations in both cases are almost identical.

Hotplug目前在动态省功耗中已经很少使用了：

1. 在动态场景中，使用isolate CPU代替，因为hotplug热插拔时延太大，在10ms+级别以上。
2. 在suspend中，使用suspend_to_idle代替，但是对于省电效果，与suspend拔除core的效果是否一致，待确定。影响手机亮屏时间。

上面五种power state进入和退出时延都是递增关系，对性能的影响大小也是递增的。所以如何进入不同的idle level state是power management核心。

对于CPU的idle power management的策略是cpuidle governor。