Verilog HDL in one day Part-III

Always Blocks

As the name suggests, an always block executes always, unlike initial blocks which execute only once (at the beginning of simulation). 

A second difference is that an always block should have a sensitive list or a delay associated with it.

正如其名字暗示的，always 块将总是不停地在执行。与initial块不同的（initial block只在simulation开始时执行一次）。

另一个不同是always block 应该有一个感应表或者与之相关的延迟。

The sensitive list is the one which tells the always block when to execute the block of code, as shown in the figure below. 

The @ symbol after reserved word ' always', indicates that the block will be triggered "at" the condition in parenthesis after symbol @.

这个感应表示告诉always block 什么时候执行其代码块，正如下面的图标所示。

这个在保留字always之后的@符号表明always block将在@符号后括号中的条件成立时，触发。

One important note about always block: it can not drive wire data type, but can drive reg and integer data types.

关于always block值得注意的一点是： 它不能被wire数据类型驱动，只能被reg类型和integer数据类型。  

 1 always  @ (a or b or sel)
 2 begin
 3   y = 0;
 4   if (sel == 0) begin
 5     y = a;
 6   end else begin
 7     y = b;
 8   end
 9 end

You could download file one_day9.v here  

The above example is a 2:1 mux, with input a and b; sel is the select input and y is the mux output. In any combinational logic, output changes whenever input changes. This theory when applied to always blocks means that the code inside always blocks needs to be executed whenever the input variables (or output controlling variables) change. These variables are the ones included in the sensitive list, namely a, b and sel.

上面的的例子是一个以a、b作为输入的2选1的选择器；其中 sel是输入选择信号，y是多路选择器的输出。

在任何组合逻辑电路中，只要输入改变，输出就会改变。这个原理用于always block，意味着，当输入变量（或者控制输出的变量）改变时，always block中的代码将被执行。

这些变量是是包含在@(...)感应表中变量，命名为 a, b, 和sel。 

There are two types of sensitive list: level sensitive (for combinational circuits) and edge sensitive (for flip-flops). The code below is the same 2:1 Mux but the output y is now a flip-flop output.

有两种类型的感应表：组合电路的电平感应（level sensitive）和触发器的(时序电路）边沿感应（edge sensitive）。下面的代码是同样的一个2选1的多路选择器，但其输出是一个

触发器的输出。  

 1 always  @ (posedge clk )
 2 if (reset == 0) begin
 3   y <= 0;
 4 end else if (sel == 0) begin
 5   y <= a;
 6 end else begin
 7   y <= b;
 8 end

You could download file one_day10.v here  

We normally have to reset flip-flops, thus every time the clock makes the transition from 0 to 1 (posedge), we check if reset is asserted (synchronous reset), then we go on with normal logic. If we look closely we see that in the case of combinational logic we had "=" for assignment, and for the sequential block we had the "<=" operator. Well, "=" is blocking assignment and "<=" is nonblocking assignment. "=" executes code sequentially inside a begin / end, whereas nonblocking "<=" executes in parallel.

我们一般要将触发器复位。但是，每次当时钟发生从0到1的跳变时（即上升沿到来时），我们检查reset复位是否设置（同步复位设置），接着进行正常的逻辑。

如果我们在仔细的观察一下，会发现在组合逻辑中我们使用=进行赋值，然而在时序块（sequential block）中我们使用<=操作符。而 = 是阻塞赋值（blocking assignment），

而 <=是非阻塞赋值（nonblocking assignment）。= 在一个begin、end中顺序执行，然而非阻塞的<=的执行是并行的。

We can have an always block without sensitive list, in this case we need to have a delay as shown in the code below.

我们可以使用一个没有感应表的always block。在这种情形下，我需要有个时间延迟，如下面的代码块。

  

 1 always  begin
 2    #5  clk = ~clk;
 3 end

You could download file one_day11.v here  

#5 in front of the statement delays its execution by 5 time units.

语句前的#5将延迟该语句在5个时间单位之后，进行执行。

  

  Assign Statement   //赋值语句

An assign statement is used for modeling only combinational logic and it is executed continuously. So the assign statement is called 'continuous assignment statement' as there is no sensitive list.

赋值语句只用于组合逻辑建模，其执行是连续的。因此，当没有感应表时，赋值语句也称为连续赋值语句。

  

 1 assign out = (enable) ? data : 1'bz;

You could download file one_day12.v here  

The above example is a tri-state buffer. When enable is 1, data is driven to out, else out is pulled to high-impedance. We can have nested conditional operators to construct mux, decoders and encoders.

上面的例子是一个三态缓冲区。当enable = 1， 用data驱动out，否则，out被上拉为高阻态。我们可以使用嵌套的条件操作符构建多路复用器、解码器和编码器。

  

 1 assign out = data;

You could download file one_day13.v here  

This example is a simple buffer. //这个例子是个简单的缓冲区。

  

  Task and Function //任务和函数

When repeating the same old things again and again, Verilog, like any other programming language, provides means to address repeated used code, these are called Tasks and Functions. I wish I had something similar for webpages, just call it to print this programming language stuff again and again.

再重复一遍，Verilog HDL和其他的编程语言一样，提供了可复用的代码的方法，这些代码称之为Task和Function，任务和函数。

  

Code below is used for calculating even parity.  //下面的代码用来计算偶校验

  1 function parity;
  2 input [31:0] data;
  3 integer i;
  4 begin
  5   parity = 0;
  6   for (i= 0; i < 32; i = i + 1) begin
  7     parity = parity ^ data[i];
  8   end
  9 end
 10 endfunction

You could download file one_day14.v here  

Functions and tasks have the same syntax; one difference is that tasks can have delays, whereas functions can not have any delay. 

This means that function can be used for modeling combinational logic.

函数function 和 任务task 有着相同的语法；不同的一点是任务task可以有时延；然而函数function没有任何时延。

这就意味着函数function可以用来为组合逻辑建模。  

A second difference is that functions can return a value, whereas tasks can not.

另一个区别是， 函数function可以返回一个值， 但是任务task不能返回值。

  

 

the original link:http://www.asic-world.com/verilog/verilog_one_day3.html