Art of Writing TestBenches （of Verilog HDL） Part - II

		Writing a TestBench  //写一个测试用例
		First step of any testbench creation is building a dummy template which basically declares inputs to DUT as reg and outputs from DUT as wire, then instantiates the DUT as shown in the code below. Note that there is no port list for the test bench. 创建一个测试基准程序的第一步是建立一个虚拟的模板，其中声明了DUT的reg类型的输入，DUT的wire类型的输出，接着实例化该DUT。如下面的code所示。 在测试基准程序中没有端口列表
		Test Bench //测试基准
		1 module counter_tb; 2 reg clk, reset, enable; 3 wire [3:0] count; 4 5 counter U0 ( 6 .clk (clk), 7 .reset (reset), 8 .enable (enable), 9 .count (count) 10 ); 11 12 endmodule You could download file counter_tb1.v here
		Next step would be to add clock generator logic: this is straight forward, as we know how to generate a clock.  下一步是添加clock产生器逻辑，正如我们所知道的如何添加一个时钟。 Before we add a clock generator we need to drive all the inputs to DUT to some known state as shown in the code below. 为了驱动DUT到某个确定的状态，我将添加一个时钟产生器，如下所示。
		Test Bench with Clock generator  //带时钟产生器的测试基准程序
		1 module counter_tb; 2 reg clk, reset, enable; 3 wire [3:0] count; 4 5 counter U0 ( 6 .clk (clk), 7 .reset (reset), 8 .enable (enable), 9 .count (count) 10 ); 11 12 initial 13 begin 14 clk = 0; 15 reset = 0; 16 enable = 0; 17 end 18 19 always 20 #5 clk = ! clk; 21 22 endmodule You could download file counter_tb2.v here
		An initial block in Verilog is executed only once, thus simulator sets the value of clk, reset and enable to 0; by looking at the counter code (of course you will be referring to the DUT specs) could be found that driving 0 makes all these signals disabled. 一个在Verilog HDL中initial block只执行一次，所以simulator将clk， reset，enable的值都设置为0.
		There are many ways to generate a clock: one could use a forever loop inside an initial block as an alternative to the above code. You could a add parameter or use `define to control the clock frequency. You may write a complex clock generator, where we could introduce PPM (Parts per million, clock width drift), then control the duty cycle. All the above depends on the specs of the DUT and the creativity of a "Test Bench Designer". 有许多方式可以产生时钟。可以使用一个在initial中的forever语句作为上面代码的的一个替代。 你可以通过一个添加一个参数或者通过使用define来控制clock的频率。你可能要写一个复杂的时钟产生器，我们可以引入PPM（parts per million ，clock width drift）从而控制任务周期。 所有的这些都依赖于DUT的规格说明书和测试基准程序设计者的创造力。
		At this point, you would like to test if the testbench is generating the clock correctly: well you can compile it with any Verilog simulator. You need to give command line options as shown below. 在这时， 你将测试这个基准是否产生正确的时钟。同样，你可以用verilog的仿真器编译。你需要下面的命令行:
		C:\www.asic-world.com\veridos counter.v counter_tb.v
		Of course it is a very good idea to keep file names the same as the module name. Ok, coming back to compiling, you will see that the simulator does print anything on screen, or dump any waveform. Thus we need to add support for all the above as shown in the code below.
		Test Bench continues...
		1 module counter_tb; 2 reg clk, reset, enable; 3 wire [3:0] count; 4 5 counter U0 ( 6 .clk (clk), 7 .reset (reset), 8 .enable (enable), 9 .count (count) 10 ); 11 12 initial begin 13 clk = 0; 14 reset = 0; 15 enable = 0; 16 end 17 18 always 19 #5 clk = ! clk; 20 21 initial begin 22 $dumpfile ("counter.vcd"); 23 $dumpvars; 24 end 25 26 initial begin 27 $display("\t\ttime,\tclk,\treset,\tenable,\tcount"); 28 $monitor("%d,\t%b,\t%b,\t%b,\t%d",$time, clk,reset,enable,count); 29 end 30 31 initial 32 #100 $finish; 33 34 //Rest of testbench code after this line 35 36 endmodule You could download file counter_tb3.v here
		$dumpfile is used for specifying the file that the simulator will use to store the waveform, that can be used later using a waveform viewer. (Please refer to the tools section for freeware versions of viewers.)  $dumpvars basically instructs the Verilog compiler to start dumping all the signals to "counter.vcd". $dumpfile: 指派那个用来存储仿真器产生的波形的文件，它可以使用波形查看器查看。 $dumpvar将指示Verilog 编译器开始转储所有的信号到counter.vcd。
		$display is used for printing text or variables to stdout (screen), \t is for inserting tabs. The syntax is the same as for printf C language.  //输出到stdout，屏幕或者标准输出。 //$monitor 追踪其参数的变化 $monitor in the second line is a bit different:  $monitor keeps track of changes to the variables that are in the list (clk, reset, enable, count).  Whenever any of them changes, it prints their value, in the respective radix specified.
		$finish结束仿真。 $finish is used for terminating the simulation after #100 time units (note: all the initial, always blocks start execution at time 0).
		Now that we have written the basic skeleton, let's compile and see what we have just coded. Output of the simulator is shown below.
		C:\www.asic-world.com>veridos counter.v counter_tb.v VeriWell for Win32 HDL Version 2.1.4 Fri Jan 17 21:33:25 2003 This is a free version of the VeriWell for Win32 Simulator Distribute this freely; call 1-800-VERIWELL for ordering information See the file "!readme.1st" for more information Copyright (c) 1993-97 Wellspring Solutions, Inc. All rights reserved Memory Available: 0 Entering Phase I... Compiling source file : counter.v Compiling source file : counter_tb.v The size of this model is [2%, 5%] of the capacity of the free version Entering Phase II... Entering Phase III... No errors in compilation Top-level modules: counter_tb time clk, reset, enable, count 0, 0, 0, 0, x 5, 1, 0, 0, x 10, 0, 0, 0, x 15, 1, 0, 0, x 20, 0, 0, 0, x 25, 1, 0, 0, x 30, 0, 0, 0, x 35, 1, 0, 0, x 40, 0, 0, 0, x 45, 1, 0, 0, x 50, 0, 0, 0, x 55, 1, 0, 0, x 60, 0, 0, 0, x 65, 1, 0, 0, x 70, 0, 0, 0, x 75, 1, 0, 0, x 80, 0, 0, 0, x 85, 1, 0, 0, x 90, 0, 0, 0, x 95, 1, 0, 0, x Exiting VeriWell for Win32 at time 100 0 Errors, 0 Warnings, Memory Used: 0 Compile time = 0.0 Load time = 0.0 Simulation time = 0.1 Normal exit Thank you for using VeriWell for Win32

the above original link:http://www.asic-world.com/verilog/art_testbench_writing2.html