一个简单的makefile模版

1，认识几个Makefile中常见的Automatic-Variables 更多信息需参考http://www.gnu.org/software/make/manual/make.html#Automatic-Variables $@

The file name of the target of the rule. If the target is an archive member, then ‘$@’ is the name of the archive file. In a pattern rule that has multiple targets (see Introduction to Pattern Rules), ‘$@’ is the name of whichever target caused the rule's recipe to be run.

$%

The target member name, when the target is an archive member. See Archives. For example, if the target is foo.a(bar.o) then ‘$%’ is bar.o and ‘$@’ is foo.a. ‘$%’ is empty when the target is not an archive member.

$<

The name of the first prerequisite. If the target got its recipe from an implicit rule, this will be the first prerequisite added by the implicit rule (see Implicit Rules).

$?

The names of all the prerequisites that are newer than the target, with spaces between them. For prerequisites which are archive members, only the named member is used (see Archives). 

$^

The names of all the prerequisites, with spaces between them. For prerequisites which are archive members, only the named member is used (see Archives). A target has only one prerequisite on each other file it depends on, no matter how many times each file is listed as a prerequisite. So if you list a prerequisite more than once for a target, the value of $^ contains just one copy of the name. This list does not contain any of the order-only prerequisites; for those see the ‘$|’ variable, below. 

2，认识几个Makefile中常见的Functions

更多信息需参考 http://www.gnu.org/software/make/manual/make.html#Functions

$(patsubst pattern,replacement,text) Finds whitespace-separated words in text that match pattern and replaces them with replacement. Here pattern may contain a ‘%’ which acts as a wildcard, matching any number of any characters within a word. If replacement also contains a ‘%’, the ‘%’ is replaced by the text that matched the ‘%’ in pattern. Only the first ‘%’ in the pattern and replacement is treated this way; any subsequent ‘%’ is unchanged.


$(notdir names...) Extracts all but the directory-part of each file name in names. If the file name contains no slash, it is left unchanged. Otherwise, everything through the last slash is removed from it.

A file name that ends with a slash becomes an empty string. This is unfortunate, because it means that the result does not always have the same number of whitespace-separated file names as the argument had; but we do not see any other valid alternative.

$(wildcard pattern) The argument pattern is a file name pattern, typically containing wildcard characters (as in shell file name patterns). The result of wildcard is a space-separated list of the names of existing files that match the pattern. 


3，一个简单的样例

#simple makefile template V0.1 2012-05-01

#Define some environment arguments
WORK_DIR=$(HOME)/Work/TestMake
BIN_DIR=$(WORK_DIR)/bin
INC_DIR=$(WORK_DIR)/include
SRC_DIR=$(WORK_DIR)/source
LIB_DIR=$(WORK_DIR)/lib
TARGET=$(BIN_DIR)/a.out

#Define some compile options
CC=g++
CFLAGS=-g -O2
INC_FLAGS=-I/usr/local/include -I$(INC_DIR)
LIB_FLAGS=-L/usr/local/lib -L$(LIB_DIR)
LINK_FLAGS=-static -lc
MACROS=

#Define the rules of compile
A_SRC=$(wildcard $(SRC_DIR)/adir/*.c $(SRC_DIR)/adir/*.cpp)
B_SRC=$(wildcard $(SRC_DIR)/bdir/*.c $(SRC_DIR)/bdir/*.cpp)
ROOT_SRC=$(wildcard $(SRC_DIR)/*.c $(SRC_DIR)/*.cpp)
A_OBJS=$(patsubst %.c, %.o, $(patsubst %.cpp, %.o, $(A_SRC)))
B_OBJS=$(patsubst %.c, %.o, $(patsubst %.cpp, %.o, $(B_SRC)))
ROOT_OBJS=$(patsubst %.c, %.o, $(patsubst %.cpp, %.o, $(ROOT_SRC)))

OBJS=$(A_OBJS) $(B_OBJS) $(ROOT_OBJS)

%.o : %.c
        rm -f $@
        $(CC) $(CFLAGS) $(INC_FLAGS) -c $< -o $@

%.o : %.cpp
        rm -f $@
        $(CC) $(CFLAGS) $(INC_FLAGS) -c $< -o $@

$(TARGET):$(OBJS)
        rm -f $@
        $(CC) $(CFLAGS) $(INC_FLAGS) -o $@ $(OBJS) $(LIB_FLAGS) $(LINK_FLAGS)

clean:
        rm -f $(TARGET) $(OBJS)