LDM(ARMv6)

LDM是实现批量内存加载的汇编指令

A4.1.20    LDM(1)

LDM(1)(加载多个)加载一个非空的子集或者全部从一段连续的内存地址到通用寄存器，它对于块加载，堆栈操作和程序退出序列；

通用寄存器能够包含PC,如果这样做的话，在Arm5或Arm5之上，PC中的一个字会当做地址来处理，然后跳转到那个地址，其中被加载值的第0位决定是否以Arm或者Thumb继续执行分支指令之后的代码，类似 BX (被加载的值)指令被执行；在更早的版本中，被加载束的第0位和第1位会被忽略，类似于mov pc,(被加载的数) 被执行；

语法

LDM{ <cond> } <adressing_mode> <Rn>{!}, <registers>

<cond> 在哪一个条件下这个指令被执行，这个条件在 The condition field 章节，在A3-3页，如果条件被省略，则默认使用AL(always)

<addressing_mode>

用来描述地址模式， 4 - Load and Store Multiple 章节，在A5-41也，它决定了指令的P,U,W位

<Rn> 指定地址模式使用的基寄存器，当使用R15作为 <Rn>时，会产生未知结果；

! 设置W位时，会让指令回写修改的值到Rn寄存器，在 Addressing Mode 4 - Load and Store Multiple A5-41页中详细定义.如果! 被省略,W位是0,这个指令在这里不会改变基寄存器(不管怎样，如果这个基寄存在在<registers>,它将在值被加载时改变)

<registers>

寄存器列表，通过都好分隔并且用{和}括起来.指定的寄存器集合将被LDM指令加载

这些寄存器将被顺序加载，并且最低的寄存器存放最低的地址（开始地址），依次存放，知道最高位的寄存器存放最高位的地址，如果PC在寄存器列表中，这个指令将会跳转到PC中加载的指定地址；

i从0到15，在寄存器列表中的第i位如果是1，则代表该寄存在在寄存器列表中，否则为0，如果第0到15位全是0 ，其结果不可预料；

架构版本

所有.

异常

数据中断？

操作

MemoryAccess(B-bit, E-bit)

if ConditionPassed(cond) then

address = start_address

for i = 0 to 14

if register_list[i] == 1 then

Ri = Memory[address, 4]

address = address + 4

if register_list[15] == 1 then

value = Memory[address,4]

if(architecture version 5 or above) then

pc = value AND 0xFFFFFFFE

T Bit = value[0]

else

pc = value AND 0xFFFFFFFC

address = address + 4

assert end_address == address - 4

A4.1.20 LDM(1)

LDM(1)(Load Multiple) loads a non-empty subset, or possibly all, of the general-purpose registers from sequential memory locations. It is useful for block loads, stack operations and procedure exit sequences.

The general-purpose registers loaded can include the PC,If they do,the word loaded for the PC is treated as an address and a branch occurs to that address.In ARMv5 and abve,bit[0] of the loaded value determines whether execution continues after this branch in ARM state or in Thumb state, as though a BX(loaded_value)

 instruction had been executed(but see also The T and J bits on page A2-15 for operation on non-T variants of ARMv5).In earlier versions of the architecture,bits[1:0] of the loaded value are ignored and execution continues in ARM state, as though the instruction MOV PC,(loaded_value) had been executed.

Syntax

LDM{ <cond> } <adressing_mode> <Rn>{!}, <registers>

where

<cond> Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-3.If <cond> is omitted, the Al(always) condition is used.

<addressing_mode> Is described in addressing Mode 4 - Load and Store Multiple on page A5-41.It determines the P,U, and W bits of the instruction.

<Rn> Specifies the base register used by <addressing_mode>. Using R15 as the base register <Rn> gives an UNPREDICTABLE result.

! Set the W bit, causing the instrction to write a modified value back to its base register Rn as specified in addressing Mode 4 - Load and Stroe Multiple on page A5-41.If ! is omitted, the W bit is 0 and the instruction does not change its base register in this way.(However, if the base register is include in <registers>,it changes when a value is loaded into it)

<registers> Is a list of registers, separated by commas and surrounded by { and }. It specifies the set of registers to be loaded by the LDM instruction.

The registers are loaded in sequence, the lowest-numbered register from the lowest memory address (start_address),through to the highest-numbered register from highest memory address(end_address) .If the PC is specified in the register list (opcode bit[15] is set), the instruction causes a branch to the address (data) loaded into the PC.

For each of i = 0 to 15,bit[i] in the register_list filed of the instruction is 1 if Ri is in the list and 0 otherwise.if bits[15:0] are all zero, the result is UNPREDICTABLE.

Architecture version

All.

Exceptions

Data Abort.

Operation

MemoryAccess(B-bit, E-bit)

if ConditionPassed(cond) then

address = start_address

for i = 0 to 14

if register_list[i] == 1 then

Ri = Memory[address, 4]

address = address + 4

if register_list[15] == 1 then

value = Memory[address,4]

if(architecture version 5 or above) then

pc = value AND 0xFFFFFFFE

T Bit = value[0]

else

pc = value AND 0xFFFFFFFC

address = address + 4

assert end_address == address - 4