delay_mode
Consider the following example, test.v, which includes an instantiated module that simulates explicit delays on certain gates.`timescale 1ns/1psmodule delay(in, out1, out2, out3, out4, transport, inertial);input in;output out1, out2, out3, out4, transp
翻译
2022-02-10 19:40:35 ·
543 阅读 ·
0 评论