启动arbiter失败Oplog entry at { ts: Timestamp 1651735515000|1, t: 1 } is missing; actual entry found is

mongodb版本是:mongodb-linux-x86_64-3.4.2.tgz

操作系统:中标麒麟服务器版

问题:

查看日志,日志里面提示:

2022-05-06T14:27:50.862+0800 I REPL     [initandlisten] Did not find local voted for document at startup.
2022-05-06T14:27:50.863+0800 I REPL     [initandlisten] Replaying stored operations from { ts: Timestamp 1651735515000|1, t: 1 } (exclusive) to { ts: Timestamp 1651735955000|1, t: 1 } (inclusive).
2022-05-06T14:27:50.863+0800 F REPL     [initandlisten] Oplog entry at { ts: Timestamp 1651735515000|1, t: 1 } is missing; actual entry found is { ts: Timestamp 1651735955000|1, t: 1 }
2022-05-06T14:27:50.863+0800 I -        [initandlisten] Fatal Assertion 40292 at src/mongo/db/repl/replication_coordinator_external_state_impl.cpp 651
2022-05-06T14:27:50.863+0800 I -        [initandlisten] 

***aborting after fassert() failure

 

解决方法:

删除arb配置的data目录下面的文件后再启动即可,我配置的目录为/opt/mongodb/data_arb。

 

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Here is an example of a Verilog code for a 3-to-1 arbitration circuit: module arbiter(input [2:0] req, // Three request signals input clk, // Clock output reg grant); // Grant signal reg [1:0] state; // State variable always @(posedge clk) begin case (state) 2'b00: begin // State 0 - Wait for requests if (req[0] == 1) // If request 0 is asserted state <= 2'b01; // Move to state 1 else if (req[1] == 1) // If request 1 is asserted state <= 2'b10; // Move to state 2 end 2'b01: begin // State 1 - Grant request 0 grant <= 1; // Assert grant signal if (req[1] == 1) // If request 1 is asserted state <= 2'b10; // Move to state 2 else state <= 2'b00; // Move to state 0 end 2'b10: begin // State 2 - Grant request 1 grant <= 1; // Assert grant signal if (req[0] == 1) // If request 0 is asserted state <= 2'b01; // Move to state 1 else state <= 2'b00; // Move to state 0 end endcase end endmodule In this code, the three request signals (req) are input to the module along with the clock signal (clk), and the grant signal is output. The module has a state variable (state) which determines which request signal to grant. In the initial state (state=2'b00), the module waits for any of the three request signals to be asserted. If request 0 (req[0]) is asserted, the module moves to state 1 (2'b01) and grants request 0 by asserting the grant signal. If request 1 (req[1]) is asserted, the module moves to state 2 (2'b10) and grants request 1. Once a request is granted, the module checks the other two request signals to see if they are still asserted. If another request is asserted, the module moves to the corresponding state and grants that request. If no other requests are asserted, the module returns to the initial state and waits for a new request to be asserted.

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