PowerPC application-level instruction set

PowerPC application-level instruction set

Table 1 lists different instruction categories and the types of instructions in each.

Table 1. Instruction categories

Instruction category Base instructions
Branch branch, branch conditional, branch to LR, branch to CTR
Condition register crand, crnor, creqv, crxor, crandc, crorc, crnand, cror, CR move
Storage access load GPR/FPR, store GPR/FPR
Integer arithmetic add, subtract, negate, multiply, divide
Integer comparison compare algebraic, compare algebraic immediate, compare logical, compare logical immediate
Integer logical and, andc, nand, or, orc, nor, xor, eqv, sign extension, count leading zeros
Integer rotate/shift rotate, rotate and mask, shift left, shift right
Floating-point arithmetic add, subtract, negate, multiply, divide, square root, multiply-add, multiply-subtract, negative multiply-add, negative multiply-subtract
Floating-point comparison compare ordered, compare unordered
Floating-point conversion round to single, convert from/to integer word/doubleword
FPSCR management move to/from FPSCR, set/clear FPSCR bit, copy FPSCR field to CR
Cache control touch, zero, flush, store
Processor management system call, move to/from special purpose registers, mtcrf, mfcr

Deciphering an instruction

All instruction encodings are 32 bits in length. Bit numbering for PowerPC is the opposite of most other definitions: bit 0 is the most significant bit, and bit 31 is the least significant bit. Instructions are first decoded by the upper 6 bits in a field, called theprimary opcode. The remaining 26 bits contain fields for operand specifiers, immediate operands, and extended opcodes, and these may be reserved bits or fields. PowerPC defines the basic instruction formats listed in Table 2.

Table 2. PowerPC instruction formats

Format 0 6 11 16 21 26 30 31
D-form opcd tgt/src src/tgt immediate
X-form opcd tgt/src src/tgt src extended opcd
A-form opcd tgt/src src/tgt src src extended opcd Rc
BD-form opcd BO BI BD AA LK
I-form opcd LI AA LK
  • D-form
    This instruction format provides up to two registers as source operands, one immediate source, and up to two registers as target operands. Some variations of this instruction format use portions of the target and source register operand specifiers as immediate fields or as extended opcodes.
  • X-form
    This instruction format provides up to two registers as source operands and up to two target operands. Some variations of this instruction format use portions of the target and source operand specifiers as immediate fields or as extended opcodes.
  • A-form
    This instruction format provides up to three registers as source operands, and one target operand. Some variations of this instruction format use portions of the target and source operand specifiers as immediate fields or as extended opcodes.
  • BD-form
    This instruction format is used by the conditional branch instruction. The BO instruction field specifies the type of condition; the BI instruction field specifies which CR bit is to be used as the condition; and the BD field is used as the branch displacement. The AA bit specifies whether the branch is an absolute or relative branch. That is, the branch target address is the value of the immediate field or is the sum of the value of the immediate field and the address of the branch. The LK bit specifies whether the address of the next sequential instruction is saved in the Link Register as a return address for a subroutine call.
  • I-form
    This instruction format is used by the unconditional branch instruction. Being unconditional, the BO and BI fields of the BD format are exchanged for additional branch displacement to form the LI instruction field. This instruction format also supports the AA and LK bits in the same fashion as the BD format.

As mentioned, there are variations to these instruction formats. However, these formats best represent the makeup of most of the PowerPC instruction set encodings.

Branch instructions

PowerPC provides a set of instructions for control flow that include:

  • Both conditional and unconditional branch instructions
  • A "decrement count and branch if zero/not zero" capability
  • Absolute and relative branching
  • Branch instructions using the contents of the Link Register or Count Register to specify the branch target address

The ability to save the address of the next sequential instruction is provided on all branch instructions, including the Branch to Link Register instruction. Conditional branches allow specifying any one of the 32 Condition Register bits to be used as the condition, and to specify whether that CR bit must be equal to 0 or 1 for the branch condition to succeed.

Condition register instructions

PowerPC provides a set of instructions for performing boolean operations on specific bits of the CR as well as copying CR fields. This allows the combining of multiple branching conditions, which can reduce the number of costly conditional branches. Table 3 lists PowerPC CR logical instructions.

Table 3. PowerPC CR logical instructions

Mnemonic Instruction name
crand CR logical and
crandc CR logical and with complement
creqv CR logical equivalent
crnand CR logical not and
crnor CR logical not or
cror CR logical or
crorc CR logical or with complement
crxor CR logical xor

Integer arithmetic instructions

Many instructions exist for performing arithmetic operations, including add, subtract, negate, compare, multiply, and divide. Many forms exist for immediate values, overflow detection, and carry in and out. Multiply and divide instruction performance varies among implementations, as these are typically multi-cycle instructions. Table 4 lists PowerPC integer arithmetic instructions.

Table 4. PowerPC integer arithmetic instructions

Mnemonic Instruction name
add[o][.] add [& record OV] [& record CR0]
addc[o][.] add carrying [& record OV] [& record CR0]
adde[o][.] add extended [& record OV] [& record CR0]
addi add immediate
addis add immediate shifted
addic[.] add immediate carrying [& record CR0]
addme[o][.] add to minus one [& record OV] [& record CR0]
addze[o][.] add to zero [& record OV] [& record CR0]
divd[o][.] divide doubleword [& record OV] [& record CR0]
divdu[o][.] divide doubleword unsigned [& record OV] [& record CR0]
divw[o][.] divide word [& record OV] [& record CR0]
divwu[o][.] divide word unsigned [& record OV] [& record CR0]
mulhd[.] multiply high doubleword [& record CR0]
mulhdu[.] multiply high doubleword unsigned [& record CR0]
mulhw[.] multiply high word [& record CR0]
mulhwu[.] multiply high word unsigned [& record CR0]
mulld[o][.] multiply low doubleword [& record OV] [& record CR0]
mulli multiply low immediate
mullw[o][.] multiply low word [& record OV] [& record CR0]
neg[o][.] negate [& record OV] [& record CR0]
subf[o][.] subtract from [& record OV] [& record CR0]
subfc[o][.] subtract from carrying [& record OV] [& record CR0]
subfe[o][.] subtract from extended [& record OV] [& record CR0]
subfi subtract from immediate
subfis subtract from immediate shifted
subfic[.] subtract from immediate carrying [& record CR0]
subfme[o][.] subtract from to minus one [& record OV] [& record CR0]
subfze[o][.] subtract from to zero [& record OV] [& record CR0]

Logical, rotate, and shift instructions

PowerPC provides a complete set of logical operations, and also provides support for sign-extension and counting the number of leading zeros in a GPR. Table 5 lists PowerPC logical instructions.

Table 5. PowerPC logical instructions

Mnemonic Instruction name
and[.] and [& record CR0]
andc[.] and with complement [& record CR0]
andi. and immediate & record CR0
andis. and immediate shifted & record CR0
eqv[.] equivalent [& record CR0]
nand[.] not and [& record CR0]
nor[.] not or [& record CR0]
or[.] or [& record CR0]
orc[.] or with complement [& record CR0]
oris or immediate shifted
ori or immediate
xor[.] xor [& record CR0]
xoris xor immediate shifted
xori xor immediate
cntlzd[.] count leading zeros doubleword [& record CR0]
cntlzw[.] count leading zeros word [& record CR0]
extsb[.] extend sign byte [& record CR0]
extsh[.] extend sign halfword [& record CR0]
extsw[.] extend sign word [& record CR0]

PowerPC provides a robust and powerful set of rotate and shift operations, as listed in Table 6.

Table 6. PowerPC rotate and shift instructions

Mnemonic Instruction name
rldc[.] rotate left doubleword then clear [& record CR0]
rldcl[.] rotate left doubleword then clear left [& record CR0]
rldcr[.] rotate left doubleword then clear right [& record CR0]
rldicl[.] rotate left doubleword immediate then clear left [& record CR0]
rldicr[.] rotate left doubleword immediate then clear right [& record CR0]
rldimi[.] rotate left doubleword immediate then mask insert [& record CR0]
rlwimi[.] rotate left word immediate then mask insert [& record CR0]
rlwinm[.] rotate left word immediate then and with mask [& record CR0]
rlwnm[.] rotate left word then and with mask [& record CR0]
sld[.] shift left doubleword [& record CR0]
slw[.] shift left word [& record CR0]
srad[.] shift right doubleword [& record CR0]
sradi[.] shift right doubleword immediate [& record CR0]
sraw[.] shift right word [& record CR0]
srawi[.] shift right word immediate [& record CR0]
srd[.] shift right doubleword [& record CR0]
srw[.] shift right word [& record CR0]

Floating-point instructions

PowerPC provides a robust set of floating-point arithmetic, comparison, and conversion operations. With software support, PowerPC floating-point arithmetic is fully compliant with the ANSI/IEEE Standard 754-1985 specification. Both single-precision and double-precision floating-point formats are supported in all arithmetic and comparison operations.

While floating-point data is stored in the FPRs in double-precision format, a set of single-precision arithmetic instructions perform the arithmetic operation and round the final result to single-precision while detecting exceptions (such as exponent overflow, underflow, and inexact) that should occur with a single-precision operation.

  • A set of Load Floating-point Single instructions access the word in storage and convert that single-precision value to double-precision format before placing in the target FPR.
  • A set of Store Floating-point Single instructions convert the source operand in the source FPR into single-precision format before storing to the target word in storage.

Specific floating-point exception classes can be enabled or disabled for supporting a trapping environment. Table 7 lists the base and optional PowerPC floating-point instruction set.

Table 7. PowerPC floating-point instructions

Mnemonic Instruction name
fmr[.] FP move [& record CR1]
fneg[.] FP negate [& record CR1]
fabs[.] FP absolute value [& record CR1]
fnabs[.] FP negative absolute value [& record CR1]
fadd[s][.] FP add [single] [& record CR1]
fsub[s][.] FP subtract [single] [& record CR1]
fmul[s][.] FP multiply [single] [& record CR1]
fdiv[s][.] FP divide [single] [& record CR1]
fsqrt[s][.] FP square root [single] [& record CR1]
fmadd[s][.] FP multiply-add [single] [& record CR1]
fmsub[s][.] FP multiply-subtract [single] [& record CR1]
fnmadd[s][.] FP negative multiply-add [single] [& record CR1]
fnmsub[s][.] FP negative multiply-subtract [single] [& record CR1]
fcmpo FP compare ordered
fcmpu FP compare unordered
fsel[.] FP select [& record CR1]
frsp[.] FP round to single [& record CR1]
fcfid[.] FP convert from integer doubleword [& record CR1]
fctid[z][.] FP convert to integer doubleword [& round to zero] [& record CR1]
fctiw[z][.] FP convert to integer word [& round to zero] [& record CR1]
fres[.] FP reciprocal estimate single [& record CR1]
frsqrte[.] FP reciprocal square root estimate [& record CR1]

FPSCR manipulation instructions

Table 8 lists the base PowerPC FPSCR manipulation instruction set.

Table 8. PowerPC FPSCR manipulation instructions

Mnemonic Instruction name
mcrfs move to CR from FPSCR
mffs[.] move from FPSCR
mtfsb0[.] move to FPSCR bit 0
mtfsb1[.] move to FPSCR bit 1
mtfsf[.] move to FPSCR field
mtfsfi[.] move to FPSCR field immediate

Load and store instructions

All load and store instructions are performed using the GPRs or a GPR and an immediate field in the instruction as specifiers of the address of the storage access. An option provided for most load and store instructions is to update the base register (in other words, RA) with the data's effective address generated by the instruction.

There are instructions for the following:

  • Byte, halfword, word, and doubleword sizes
  • Moving data between GPRs or FPRs and storage
  • Moving data between GPRs or FPRs and storage

Special storage access instructions include:

  • Multiple-word load/stores 
    These are lmw and stmw, and can operate on up to 31 32-bit words.

  • String instructions
    These can operate on up to 128-byte strings.

  • Memory Synchronization instructions
    These are used to implement memory synchronization. Bit 2 (EQ bit) of the CR is set to record the successful completion of the store operation. Memsync instructions include:
    • lwarx (Load Word and Reserve Indexed)
    • ldarx (Load Doubleword and Reserve Indexed)
    • stwcx (Store Word Conditional Index)
    • stdcx (Store Doubleword Conditional Index)
    lwarx/ldarx performs a load and sets a reservation bit internal to the processor and hidden from the programming model. The associated store instruction stwcx./stdcx. performs a conditional store if the reservation bit is set and thereafter clears the reservation bit.

Stack

The PowerPC architecture has no notion of a stack for local storage. There are no push or pop instructions and no dedicated stack pointer register defined by the architecture. However, there is a software standard used for C/C++ programs called the Embedded Application Binary Interface (EABI), which defines register and memory conventions for a stack. The EABI reserves GPR1 for a stack pointer, GPR3-GPR7 for function argument passing, and GPR3 for function return values.

Assembly language programs wishing to interface to C/C++ code must follow the same standards to preserve the conventions.

Cache management instructions

The PowerPC architecture contains cache management instructions for both application-level cache accesses. Cache management instructions are listed in Table 9.

Table 9. Cache management instructions

Mnemonic Instruction name
dcbf Flush Data Cache Line
dcbst Store Data Cache Line
dcbt Touch Data Cache Line (for load)
dcbtst Touch Data Cache Line (for store)
dcbz Zero Data Cache Line
icbi Invalidate Instruction Cache Line

Take care when porting cache manipulation code to a different PowerPC implementation. Although cache instructions may be common across different implementations, cache organization and size may likely change. For example, code that makes assumptions about the cache size to perform a flush may need to be modified for other cache sizes. Also, cache initialization may vary between implementations. Some provide hardware to automatically clear cache tags, while others require software looping to invalidate cache tags.

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