</pre>DM6437 PLL分析</h1><h3><span style="font-size:18px;"><span style="font-family:KaiTi_GB2312;"> <span style="font-weight: normal;"> dm6437有两个PLL分别为PLL1和PLL2,这两个pll分别给系统的各个部分提供时钟,pll2主要是给DDR提供时钟的。系统的参考输入时钟为27Mhz。</span></span></span></h3><h3><span style="font-family:KaiTi_GB2312;font-size:18px;"> PLL1</span><span style="font-family:KaiTi_GB2312;font-size:24px;">:</span></h3><div><span style="font-family:KaiTi_GB2312;font-size:24px;"> </span><span style="font-family:KaiTi_GB2312;font-size:18px;">软件设置</span><span style="font-family:KaiTi_GB2312;font-size:18px;">pll1控制寄存器来配置属于pll1控制部分的时钟,主要由以下几个:</span></div><div><span style="font-family:KaiTi_GB2312;font-size:18px;"> SYSCLK1: CLKDIV1 Domain SYSCLK2: CLKDIV3 Domain SYSCLK3: CLKDIV6 Domain AUXCLK: CLKIN Domain OBSCLK: CLKOUT0 pin SYSCLKBP: VPBE internal clock source</span></div><div><span style="font-family:KaiTi_GB2312;font-size:18px;"> 这些时钟是通过操作pll1的PLLM和PLLDIV1, PLLDIV2, and PLLDIV3得到的。</span></div><div><span style="font-family:KaiTi_GB2312;font-size:18px;"></span></div><div><span style="font-family:KaiTi_GB2312;font-size:18px;"> <img src="https://img-blog.csdn.net/20141028140700231?watermark/2/text/aHR0cDovL2Jsb2cuY3Nkbi5uZXQvQ1JBWlkzMTE=/font/5a6L5L2T/fontsize/400/fill/I0JBQkFCMA==/dissolve/70/gravity/SouthEast" alt="" /></span></div><div><span style="font-family:KaiTi_GB2312;font-size:18px;"> 选择OSCIN输入模式,输入时钟为27mhz。</span></div><div><span style="font-family:KaiTi_GB2312;font-size:18px;"></span></div><div><span style="font-family:KaiTi_GB2312;font-size:18px;"> <img src="https://img-blog.csdn.net/20141028140923501?watermark/2/text/aHR0cDovL2Jsb2cuY3Nkbi5uZXQvQ1JBWlkzMTE=/font/5a6L5L2T/fontsize/400/fill/I0JBQkFCMA==/dissolve/70/gravity/SouthEast" alt="" /></span></div><div><span style="font-family:KaiTi_GB2312;font-size:18px;">在以下三种情况下改变pll1的时钟:</span><span style="font-family: KaiTi_GB2312;font-size:18px;">PLL1在掉电模式下(</span><span style="font-family: KaiTi_GB2312;font-size:18px;">PLLCTL寄存器中</span><span style="font-family: KaiTi_GB2312;font-size:18px;">PLLPWRDN 位为1)</span></div><div><span style="font-family:KaiTi_GB2312;font-size:18px;">1、选择合适的时钟源(CLKMODE bit in PLLCTL)</span></div><div><span style="font-family:KaiTi_GB2312;font-size:18px;">2、在改变pll1频率前,设置pll1在旁路模式</span></div><div><span style="font-family:KaiTi_GB2312;font-size:18px;"> 清除<span style="font-family: KaiTi_GB2312;font-size:18px;">PLLCTL中的PLLENSRC位,允许PLLCTL.PLLEN有效</span></span></div><div><span style="font-family:KaiTi_GB2312;font-size:18px;"> 清除PLLCTL.PLLEN位,使PLL1工作在旁路模式</span></div><div><span style="font-family:KaiTi_GB2312;font-size:18px;"> 等待合适的时间</span></div><div><span style="font-family:KaiTi_GB2312;font-size:18px;">3、清除PLLCTL.PLLRST位,复位PLL</span></div><div><span style="font-family:KaiTi_GB2312;font-size:18px;">4、设置PLLCTL.PLLDIS位为1,禁止PLL1输出</span></div><div><span style="font-family:KaiTi_GB2312;font-size:18px;">5、PLLPWRDN设置为0,工作在上电模式</span></div><div><span style="font-family:KaiTi_GB2312;font-size:18px;">6、PLLDIS设置为0,使能PLL1输出</span></div><div><span style="font-family:KaiTi_GB2312;font-size:18px;">7、等待PLL1稳定</span></div><div><span style="font-family:KaiTi_GB2312;font-size:18px;">8、设置倍频PLLM</span></div><div><span style="font-family:KaiTi_GB2312;font-size:18px;">9、设置分频系数1:3:6分频,设置PLLCMD为1</span></div><div><span style="font-family:KaiTi_GB2312;font-size:18px;">10、等待 GOSTAT 在 PLLSTAT 为0</span></div><div><span style="font-family:KaiTi_GB2312;font-size:18px;">11、设置PLLRST为1,不复位PLL1</span></div><div><span style="font-family:KaiTi_GB2312;font-size:18px;">12、等待</span></div><div><span style="font-family:KaiTi_GB2312;font-size:18px;">13、设置PLLEN为1,使得工作在PLL模式,而非旁路模式。</span></div><div><span style="font-family:KaiTi_GB2312;font-size:18px;"></span></div><h2><span style="font-family:KaiTi_GB2312;font-size:18px;">若PLLPWRDN为0,并非掉电模式下只设置PLLM</span></h2><div><span style="font-family:KaiTi_GB2312;font-size:18px;">1、清除PLLCTL中的PLLENSRC位,使得PLLCTL.PLLEN有效</span></div><div><span style="font-family:KaiTi_GB2312;font-size:18px;"> 清除PLLEN位使PLL1工作在旁路模式</span></div><div><span style="font-family:KaiTi_GB2312;font-size:18px;"> 等待合适的时间</span></div><div><span style="font-family:KaiTi_GB2312;font-size:18px;">2、清楚PLLRST,使得PLL1复位</span></div><div><span style="font-family:KaiTi_GB2312;font-size:18px;">3、清除PLLDIS位,允许PLL1输出</span></div><div><span style="font-family:KaiTi_GB2312;font-size:18px;">4、设置倍频系数PLLM</span></div><div><span style="font-family:KaiTi_GB2312;font-size:18px;">5、设置PLLDIV1, PLLDIV2, and PLLDIV3</span></div><div><span style="font-family:KaiTi_GB2312;font-size:18px;">6、等待</span></div><div><span style="font-family:KaiTi_GB2312;font-size:18px;">7、设置PLLRST使得不复位</span></div><div><span style="font-family:KaiTi_GB2312;font-size:18px;">8、等待</span></div><div><span style="font-family:KaiTi_GB2312;font-size:18px;">9、设置PLLEN使得不工作在旁路模式</span></div><div><span style="font-family:KaiTi_GB2312;font-size:24px;"> </span></div><div><span style="font-family:KaiTi_GB2312;font-size:24px;">PLL2设置</span></div><div><span style="font-family:KaiTi_GB2312;"><span style="font-size:18px;">PLL2给ddr以及vpbe提供系统时钟</span></span><span style="font-size:24px; font-family: KaiTi_GB2312;"> </span></div><div><span style="font-family:KaiTi_GB2312;font-size:18px;">•SYSCLK1: DDR2 PHY•SYSCLK2: VPSS•SYSCLKBP: DDR2 VTP</span></div><div><span style="font-family:KaiTi_GB2312;font-size:18px;"><img src="https://img-blog.csdn.net/20141028161039416?watermark/2/text/aHR0cDovL2Jsb2cuY3Nkbi5uZXQvQ1JBWlkzMTE=/font/5a6L5L2T/fontsize/400/fill/I0JBQkFCMA==/dissolve/70/gravity/SouthEast" alt="" /></span></div><div><span style="font-family:KaiTi_GB2312;font-size:18px;">系统时钟SYSCLK1输出默认被2分频,假设系统时钟为27m,那么倍频为20,所以PLL2_SYSCLK1为270m,所以到达ddr的时钟为270/2=135mhz,SYSCLK2为540/10=54mhz提供给vpss。</span></div><div><span style="font-family:KaiTi_GB2312;font-size:18px;">设置pll2的方法和设置pll1的方法一样。</span></div><div><span style="font-family:KaiTi_GB2312;font-size:18px;"></span></div><div><span style="font-family:KaiTi_GB2312;font-size:18px;">接下来通过程序分析如何设置PLL:</span></div><div><span style="font-family:KaiTi_GB2312;font-size:18px;">以下是dm6437gel文件中的一段代码:</span></div><div><span style="font-family:KaiTi_GB2312;font-size:18px;"></span><pre name="code" class="html">
/* ------------------------------------------------------------------------ *
* *
* setup_pll_1( ) *
* *
* clock_source <- 0: Onchip Oscillator *
* 1: External Clock *
* *
* pll_mult <- 21: 22x Multiplier * 27MHz Clk = 594 MHz *
* *
* ------------------------------------------------------------------------ */
setup_pll_1( int clock_source, int pll_mult )
{
unsigned int* pll_ctl = ( unsigned int* )( 0x01c40900 );
unsigned int* pll_pllm = ( unsigned int* )( 0x01c40910 );
unsigned int* pll_cmd = ( unsigned int* )( 0x01c40938 );
unsigned int* pll_stat = ( unsigned int* )( 0x01c4093c );
unsigned int* pll_div1 = ( unsigned int* )( 0x01c40918 );
unsigned int* pll_div2 = ( unsigned int* )( 0x01c4091c );
unsigned int* pll_div3 = ( unsigned int* )( 0x01c40920 );
unsigned int* pll_bpdiv = ( unsigned int* )( 0x01c4092c );
int pll1_freq = 27 * ( pll_mult + 1 );//<span style="font-family: Arial, Helvetica, sans-serif;">pll_mult 设置为21,pll1_freq=594mhz</span>
int div1 = 0;
int div2 = 2;
int div3 = 5;
int bypass_div = 0;
int power_up_pll = ( *pll_ctl & 0x0002 ) >> 1;//查看在掉电还是上电模式
GEL_TextOut( "Setup PLL1 " );
/*
* Step 0 - Ignore request if the PLL is already set as is
*/
if ( ( ( *pll_ctl & 0x0100 ) >> 8 ) == clock_source )
{
if ( ( *pll_pllm & 0x3f ) == ( pll_mult & 0x3f ) )
{
if ( ( ( *pll_div1 & 0x1f ) == div1 )
|| ( ( *pll_div2 & 0x1f ) == div2 )
|| ( ( *pll_div3 & 0x1f ) == div3 ) )
{
GEL_TextOut( "(DSP = %d MHz + ",,,,, pll1_freq / ( div1 + 1 ) );
GEL_TextOut( "SYSCLK2 = %d MHz + ",,,,, pll1_freq / ( div2 + 1 ) );
GEL_TextOut( "SYSCLK3 = %d MHz + ",,,,, pll1_freq / ( div3 + 1 ) );
if ( clock_source == 0 )
GEL_TextOut( "Onchip Oscillator)... " );
else
GEL_TextOut( "External Clock)... " );
GEL_TextOut( "[Already Set]\n" );
return;
}
}
}
/*
* Step 1 - Set clock mode在上电模式下选择时钟源,这里为0
*/
if ( power_up_pll == 1 )
{
GEL_TextOut( "(Powering up PLL)... " );
if ( clock_source == 0 )
*pll_ctl &= ~0x0100; // Onchip Oscillator
else
*pll_ctl |= 0x0100; // External Clock
}
/*
* Step 2 - Set PLL to bypass
* - Wait for PLL to stabilize
*/
*pll_ctl &= ~0x0021;//PLLENSRC为0,PLLEN为0
_wait( 150 );
/*
* Step 3 - Reset PLL
*/
*pll_ctl &= ~0x0008;//PLLRST为0
/*
* Step 4 - Disable PLL
* Step 5 - Powerup PLL
* Step 6 - Enable PLL
* Step 7 - Wait for PLL to stabilize
*/
if ( power_up_pll == 1 )
{
*pll_ctl |= 0x0010; // Disable PLL,PLLDIS为1,禁止输出
*pll_ctl &= ~0x0002; // Power up PLL,PLLPWERDN为0,上电模式
*pll_ctl &= ~0x0010; // Enable PLL,使能pll输出
_wait( 150 ); // Wait for PLL to stabilize
}
else
*pll_ctl &= ~0x0010; // Enable PLL
/*
* Step 8 - Load PLL multiplier
*/
*pll_pllm = pll_mult & 0x3f;//设置倍频系数为21
/*
* Step 9 - Load PLL dividers ( must be in a 1/3/6 ratio )
* 1:DSP, 2:SCR,EMDA,VPSS, 3:Peripherals
*/
*pll_bpdiv = 0x8000 | bypass_div; // Bypass divider
*pll_div1 = 0x8000 | div1; // Divide-by-1 or Divide-by-2设置分频系数
*pll_div2 = 0x8000 | div2; // Divide-by-3 or Divide-by-6
*pll_div3 = 0x8000 | div3; // Divide-by-6 or Divide-by-12
*pll_cmd |= 0x0001; // Set phase alignment使设置的值有效
while( ( *pll_stat & 1 ) != 0 );// Wait for phase alignment等待状态
/*
* Step 10 - Wait for PLL to reset ( 2000 cycles )
* Step 11 - Release from reset
*/
_wait( 2000 );
*pll_ctl |= 0x0008;//使得pll不复位
/*
* Step 12 - Wait for PLL to re-lock ( 2000 cycles )
* Step 13 - Switch out of BYPASS mode
*/
_wait( 2000 );
*pll_ctl |= 0x0001;//使得不工作在旁路模式下
pll1_freq = 27 * ( ( *pll_pllm & 0x3f ) + 1 );
div1 = ( *pll_div1 & 0x1f );
div2 = ( *pll_div2 & 0x1f );
div3 = ( *pll_div3 & 0x1f );
GEL_TextOut( "(DSP = %d MHz + ",,,,, pll1_freq / ( div1 + 1 ) );
GEL_TextOut( "SYSCLK2 = %d MHz + ",,,,, pll1_freq / ( div2 + 1 ) );
GEL_TextOut( "SYSCLK3 = %d MHz + ",,,,, pll1_freq / ( div3 + 1 ) );
if ( clock_source == 0 )
GEL_TextOut( "Onchip Oscillator)... " );
else
GEL_TextOut( "External Clock)... " );
GEL_TextOut( "[Done]\n" );
}
</pre>DM6437 PLL分析</h1><h3><span style="font-size:18px;"><span style="font-family:KaiTi_GB2312;"> <span style="font-weight: normal;"> dm6437有两个PLL分别为PLL1和PLL2,这两个pll分别给系统的各个部分提供时钟,pll2主要是给DDR提供时钟的。系统的参考输入时钟为27Mhz。</span></span></span></h3><h3><span style="font-family:KaiTi_GB2312;font-size:18px;"> PLL1</span><span style="font-family:KaiTi_GB2312;font-size:24px;">:</span></h3><div><span style="font-family:KaiTi_GB2312;font-size:24px;"> </span><span style="font-family:KaiTi_GB2312;font-size:18px;">软件设置</span><span style="font-family:KaiTi_GB2312;font-size:18px;">pll1控制寄存器来配置属于pll1控制部分的时钟,主要由以下几个:</span></div><div><span style="font-family:KaiTi_GB2312;font-size:18px;"> SYSCLK1: CLKDIV1 Domain SYSCLK2: CLKDIV3 Domain SYSCLK3: CLKDIV6 Domain AUXCLK: CLKIN Domain OBSCLK: CLKOUT0 pin SYSCLKBP: VPBE internal clock source</span></div><div><span style="font-family:KaiTi_GB2312;font-size:18px;"> 这些时钟是通过操作pll1的PLLM和PLLDIV1, PLLDIV2, and PLLDIV3得到的。</span></div><div><span style="font-family:KaiTi_GB2312;font-size:18px;"></span></div><div><span style="font-family:KaiTi_GB2312;font-size:18px;"> <img src="https://img-blog.csdn.net/20141028140700231?watermark/2/text/aHR0cDovL2Jsb2cuY3Nkbi5uZXQvQ1JBWlkzMTE=/font/5a6L5L2T/fontsize/400/fill/I0JBQkFCMA==/dissolve/70/gravity/SouthEast" alt="" /></span></div><div><span style="font-family:KaiTi_GB2312;font-size:18px;"> 选择OSCIN输入模式,输入时钟为27mhz。</span></div><div><span style="font-family:KaiTi_GB2312;font-size:18px;"></span></div><div><span style="font-family:KaiTi_GB2312;font-size:18px;"> <img src="https://img-blog.csdn.net/20141028140923501?watermark/2/text/aHR0cDovL2Jsb2cuY3Nkbi5uZXQvQ1JBWlkzMTE=/font/5a6L5L2T/fontsize/400/fill/I0JBQkFCMA==/dissolve/70/gravity/SouthEast" alt="" /></span></div><div><span style="font-family:KaiTi_GB2312;font-size:18px;">在以下三种情况下改变pll1的时钟:</span><span style="font-family: KaiTi_GB2312;font-size:18px;">PLL1在掉电模式下(</span><span style="font-family: KaiTi_GB2312;font-size:18px;">PLLCTL寄存器中</span><span style="font-family: KaiTi_GB2312;font-size:18px;">PLLPWRDN 位为1)</span></div><div><span style="font-family:KaiTi_GB2312;font-size:18px;">1、选择合适的时钟源(CLKMODE bit in PLLCTL)</span></div><div><span style="font-family:KaiTi_GB2312;font-size:18px;">2、在改变pll1频率前,设置pll1在旁路模式</span></div><div><span style="font-family:KaiTi_GB2312;font-size:18px;"> 清除<span style="font-family: KaiTi_GB2312;font-size:18px;">PLLCTL中的PLLENSRC位,允许PLLCTL.PLLEN有效</span></span></div><div><span style="font-family:KaiTi_GB2312;font-size:18px;"> 清除PLLCTL.PLLEN位,使PLL1工作在旁路模式</span></div><div><span style="font-family:KaiTi_GB2312;font-size:18px;"> 等待合适的时间</span></div><div><span style="font-family:KaiTi_GB2312;font-size:18px;">3、清除PLLCTL.PLLRST位,复位PLL</span></div><div><span style="font-family:KaiTi_GB2312;font-size:18px;">4、设置PLLCTL.PLLDIS位为1,禁止PLL1输出</span></div><div><span style="font-family:KaiTi_GB2312;font-size:18px;">5、PLLPWRDN设置为0,工作在上电模式</span></div><div><span style="font-family:KaiTi_GB2312;font-size:18px;">6、PLLDIS设置为0,使能PLL1输出</span></div><div><span style="font-family:KaiTi_GB2312;font-size:18px;">7、等待PLL1稳定</span></div><div><span style="font-family:KaiTi_GB2312;font-size:18px;">8、设置倍频PLLM</span></div><div><span style="font-family:KaiTi_GB2312;font-size:18px;">9、设置分频系数1:3:6分频,设置PLLCMD为1</span></div><div><span style="font-family:KaiTi_GB2312;font-size:18px;">10、等待 GOSTAT 在 PLLSTAT 为0</span></div><div><span style="font-family:KaiTi_GB2312;font-size:18px;">11、设置PLLRST为1,不复位PLL1</span></div><div><span style="font-family:KaiTi_GB2312;font-size:18px;">12、等待</span></div><div><span style="font-family:KaiTi_GB2312;font-size:18px;">13、设置PLLEN为1,使得工作在PLL模式,而非旁路模式。</span></div><div><span style="font-family:KaiTi_GB2312;font-size:18px;"></span></div><h2><span style="font-family:KaiTi_GB2312;font-size:18px;">若PLLPWRDN为0,并非掉电模式下只设置PLLM</span></h2><div><span style="font-family:KaiTi_GB2312;font-size:18px;">1、清除PLLCTL中的PLLENSRC位,使得PLLCTL.PLLEN有效</span></div><div><span style="font-family:KaiTi_GB2312;font-size:18px;"> 清除PLLEN位使PLL1工作在旁路模式</span></div><div><span style="font-family:KaiTi_GB2312;font-size:18px;"> 等待合适的时间</span></div><div><span style="font-family:KaiTi_GB2312;font-size:18px;">2、清楚PLLRST,使得PLL1复位</span></div><div><span style="font-family:KaiTi_GB2312;font-size:18px;">3、清除PLLDIS位,允许PLL1输出</span></div><div><span style="font-family:KaiTi_GB2312;font-size:18px;">4、设置倍频系数PLLM</span></div><div><span style="font-family:KaiTi_GB2312;font-size:18px;">5、设置PLLDIV1, PLLDIV2, and PLLDIV3</span></div><div><span style="font-family:KaiTi_GB2312;font-size:18px;">6、等待</span></div><div><span style="font-family:KaiTi_GB2312;font-size:18px;">7、设置PLLRST使得不复位</span></div><div><span style="font-family:KaiTi_GB2312;font-size:18px;">8、等待</span></div><div><span style="font-family:KaiTi_GB2312;font-size:18px;">9、设置PLLEN使得不工作在旁路模式</span></div><div><span style="font-family:KaiTi_GB2312;font-size:24px;"> </span></div><div><span style="font-family:KaiTi_GB2312;font-size:24px;">PLL2设置</span></div><div><span style="font-family:KaiTi_GB2312;"><span style="font-size:18px;">PLL2给ddr以及vpbe提供系统时钟</span></span><span style="font-size:24px; font-family: KaiTi_GB2312;"> </span></div><div><span style="font-family:KaiTi_GB2312;font-size:18px;">•SYSCLK1: DDR2 PHY•SYSCLK2: VPSS•SYSCLKBP: DDR2 VTP</span></div><div><span style="font-family:KaiTi_GB2312;font-size:18px;"><img src="https://img-blog.csdn.net/20141028161039416?watermark/2/text/aHR0cDovL2Jsb2cuY3Nkbi5uZXQvQ1JBWlkzMTE=/font/5a6L5L2T/fontsize/400/fill/I0JBQkFCMA==/dissolve/70/gravity/SouthEast" alt="" /></span></div><div><span style="font-family:KaiTi_GB2312;font-size:18px;">系统时钟SYSCLK1输出默认被2分频,假设系统时钟为27m,那么倍频为20,所以PLL2_SYSCLK1为270m,所以到达ddr的时钟为270/2=135mhz,SYSCLK2为540/10=54mhz提供给vpss。</span></div><div><span style="font-family:KaiTi_GB2312;font-size:18px;">设置pll2的方法和设置pll1的方法一样。</span></div><div><span style="font-family:KaiTi_GB2312;font-size:18px;"></span></div><div><span style="font-family:KaiTi_GB2312;font-size:18px;">接下来通过程序分析如何设置PLL:</span></div><div><span style="font-family:KaiTi_GB2312;font-size:18px;">以下是dm6437gel文件中的一段代码:</span></div><div><span style="font-family:KaiTi_GB2312;font-size:18px;"></span><pre name="code" class="html">
/* ------------------------------------------------------------------------ *
* *
* setup_pll_1( ) *
* *
* clock_source <- 0: Onchip Oscillator *
* 1: External Clock *
* *
* pll_mult <- 21: 22x Multiplier * 27MHz Clk = 594 MHz *
* *
* ------------------------------------------------------------------------ */
setup_pll_1( int clock_source, int pll_mult )
{
unsigned int* pll_ctl = ( unsigned int* )( 0x01c40900 );
unsigned int* pll_pllm = ( unsigned int* )( 0x01c40910 );
unsigned int* pll_cmd = ( unsigned int* )( 0x01c40938 );
unsigned int* pll_stat = ( unsigned int* )( 0x01c4093c );
unsigned int* pll_div1 = ( unsigned int* )( 0x01c40918 );
unsigned int* pll_div2 = ( unsigned int* )( 0x01c4091c );
unsigned int* pll_div3 = ( unsigned int* )( 0x01c40920 );
unsigned int* pll_bpdiv = ( unsigned int* )( 0x01c4092c );
int pll1_freq = 27 * ( pll_mult + 1 );//<span style="font-family: Arial, Helvetica, sans-serif;">pll_mult 设置为21,pll1_freq=594mhz</span>
int div1 = 0;
int div2 = 2;
int div3 = 5;
int bypass_div = 0;
int power_up_pll = ( *pll_ctl & 0x0002 ) >> 1;//查看在掉电还是上电模式
GEL_TextOut( "Setup PLL1 " );
/*
* Step 0 - Ignore request if the PLL is already set as is
*/
if ( ( ( *pll_ctl & 0x0100 ) >> 8 ) == clock_source )
{
if ( ( *pll_pllm & 0x3f ) == ( pll_mult & 0x3f ) )
{
if ( ( ( *pll_div1 & 0x1f ) == div1 )
|| ( ( *pll_div2 & 0x1f ) == div2 )
|| ( ( *pll_div3 & 0x1f ) == div3 ) )
{
GEL_TextOut( "(DSP = %d MHz + ",,,,, pll1_freq / ( div1 + 1 ) );
GEL_TextOut( "SYSCLK2 = %d MHz + ",,,,, pll1_freq / ( div2 + 1 ) );
GEL_TextOut( "SYSCLK3 = %d MHz + ",,,,, pll1_freq / ( div3 + 1 ) );
if ( clock_source == 0 )
GEL_TextOut( "Onchip Oscillator)... " );
else
GEL_TextOut( "External Clock)... " );
GEL_TextOut( "[Already Set]\n" );
return;
}
}
}
/*
* Step 1 - Set clock mode在上电模式下选择时钟源,这里为0
*/
if ( power_up_pll == 1 )
{
GEL_TextOut( "(Powering up PLL)... " );
if ( clock_source == 0 )
*pll_ctl &= ~0x0100; // Onchip Oscillator
else
*pll_ctl |= 0x0100; // External Clock
}
/*
* Step 2 - Set PLL to bypass
* - Wait for PLL to stabilize
*/
*pll_ctl &= ~0x0021;//PLLENSRC为0,PLLEN为0
_wait( 150 );
/*
* Step 3 - Reset PLL
*/
*pll_ctl &= ~0x0008;//PLLRST为0
/*
* Step 4 - Disable PLL
* Step 5 - Powerup PLL
* Step 6 - Enable PLL
* Step 7 - Wait for PLL to stabilize
*/
if ( power_up_pll == 1 )
{
*pll_ctl |= 0x0010; // Disable PLL,PLLDIS为1,禁止输出
*pll_ctl &= ~0x0002; // Power up PLL,PLLPWERDN为0,上电模式
*pll_ctl &= ~0x0010; // Enable PLL,使能pll输出
_wait( 150 ); // Wait for PLL to stabilize
}
else
*pll_ctl &= ~0x0010; // Enable PLL
/*
* Step 8 - Load PLL multiplier
*/
*pll_pllm = pll_mult & 0x3f;//设置倍频系数为21
/*
* Step 9 - Load PLL dividers ( must be in a 1/3/6 ratio )
* 1:DSP, 2:SCR,EMDA,VPSS, 3:Peripherals
*/
*pll_bpdiv = 0x8000 | bypass_div; // Bypass divider
*pll_div1 = 0x8000 | div1; // Divide-by-1 or Divide-by-2设置分频系数
*pll_div2 = 0x8000 | div2; // Divide-by-3 or Divide-by-6
*pll_div3 = 0x8000 | div3; // Divide-by-6 or Divide-by-12
*pll_cmd |= 0x0001; // Set phase alignment使设置的值有效
while( ( *pll_stat & 1 ) != 0 );// Wait for phase alignment等待状态
/*
* Step 10 - Wait for PLL to reset ( 2000 cycles )
* Step 11 - Release from reset
*/
_wait( 2000 );
*pll_ctl |= 0x0008;//使得pll不复位
/*
* Step 12 - Wait for PLL to re-lock ( 2000 cycles )
* Step 13 - Switch out of BYPASS mode
*/
_wait( 2000 );
*pll_ctl |= 0x0001;//使得不工作在旁路模式下
pll1_freq = 27 * ( ( *pll_pllm & 0x3f ) + 1 );
div1 = ( *pll_div1 & 0x1f );
div2 = ( *pll_div2 & 0x1f );
div3 = ( *pll_div3 & 0x1f );
GEL_TextOut( "(DSP = %d MHz + ",,,,, pll1_freq / ( div1 + 1 ) );
GEL_TextOut( "SYSCLK2 = %d MHz + ",,,,, pll1_freq / ( div2 + 1 ) );
GEL_TextOut( "SYSCLK3 = %d MHz + ",,,,, pll1_freq / ( div3 + 1 ) );
if ( clock_source == 0 )
GEL_TextOut( "Onchip Oscillator)... " );
else
GEL_TextOut( "External Clock)... " );
GEL_TextOut( "[Done]\n" );
}