The Easiest Path from ESL to Silicon

最新推荐文章于 2020-09-24 06:31:21 发布

changan2001

最新推荐文章于 2020-09-24 06:31:21 发布

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分类专栏： HLS 文章标签： path performance optimization processing debugging matlab

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AutoPilot, a powerful ESL synthesis software tool, automatically generates efficient RTL code from C, C++, or SystemC descriptions and simultaneously optimizes logic, interconnects, performance, and power, providing superior platform-based system-level synthesis capability. The behavioral design descriptions are parsed and optimized by AutoESL’s enhancements to a fully GNU compatible compiler.

AutoPilot’s core technology is an advanced ESL synthesis and optimization engine that manages large systems described in a high-level language with minimal modifications to its source code. AutoPilot’s synthesis engine performs precise platform pre-characterization that enables more informed optimizations. The characterization libraries contain delay, area and power information for resources such as ALUs, multipliers, memories, and steering logic. Layout information of the target FPGA is also utilized by the physical-aware synthesis engine. Constraints for the RTL code such as multi-cycle and false paths are automatically generated to insure design closure.

Below are more facts about AutoESL:

Technology Brief

Overview of the Technology

Platform-based communication-centric synthesis
Unified coverage of C,C++, and SystemC languages
Advanced code transformations
Highly scalable ESL optimization
Direct synthesis of single and double precision floating point operations
Black-box Xilinx FPGA core support
Automatic RTL test bench generation
Industry standard Eclipse user interface
Generates synthesizable VHDL, Verilog HDL, and SystemC code

Language Background

Which languages are supported?

Untimed ANSI-C, C++, and SystemC code

How is parallelization achieved?

Parallelization is extracted from the algorithm by examining the untimed system-level behavioral source code and using a GNU-compatible software compiler to apply advanced code transformation, optimization techniques such as loop unrolling, if-conversion, loop flattening and data dependence analysis.
The compiler automatically employs behavior-level scheduling and resource binding on data-intensive and control-intensive algorithms that can include large memory structures
The designer can also specify course-grain parallelism using SystemC

Are multiple clock domains supported?

Multiple clock domains are supported

Level of Abstraction — How different is it from coding in HDL?

With AutoPilot, software written in C/C++/SystemC-code used at the system level does not have to be re-written for synthesis
Source code is written at the behavioral level versus at an RTL level
Throughput, latency and various pipeline options can be specified in a constraint file used by the synthesis engine versus explicit coding of timing and concurrency in RTL
Design of a large system is driven by behavioral- and architectural-level executable models written in C/C++/SystemC instead of hardware-specific HDL models
Much more efficient and faster evaluation of different micro-architectures, hardware and software boundaries using a high-level language
10:1 reduction in code base size using a high-level language versus HDL

Is floating point operation supported?

Yes, single and double precision floating point is supported in AutoPilot by using Xilinx floating point library and those from third parties
Mapping from float, double and single types is automatic
Automatic type conversions: single <-> double, integer <-> single/double
Floating point operators such as MULT, DIV, ADD, SUB... are supported directly
Transcendental and trigonometric functions supported directly
No modifications to the source code are required to use the libraries

Is an interface to MATLAB supported?

The C-interface mechanism in MATLAB® can be used to import a model for simulation
Integration work underway to automate process

Are standalone function libraries available?

Depending on the target FPGA, AutoPilot uses its own library for synthesis that contains objects such adders and shifters and also uses primitives such as XtremeDSP™ DSP48s slic es, embedded adders and multipliers
Users can also instantiate LogiCORE™ functionality into the library for the synthesis engine

What format is the synthesis output?

AutoPilot generates synthesizable Verilog HDL, SystemC, and VHDL RTL code
AutoPilot's design flow automatically generates all of the files necessary for FPGA implementation using Xilinx XST, ISE™, and Synplicity tools.

Quality of results / Optimization scenarios

AutoPilot synthesis from software provides over 10X code base size reduction and enables reuse of software IP
100-1000X simulation speed-up possible by using software behavioral models at top-level of the design that enables more system-level trade offs and verification prior to committing to hardware
User constraints for area and time steer the the synthesis engine to quickly provide many different solutions that are used to decide upon the optimum architecture
C-code for an MPEG4 decoder was synthesized by AutoPilot that achieved the same performance (125 MHz) with a 91 percent smaller code base than the same implementation in RTL (5200 lines of C vs. 57000 lines of VHDL)
A Black-Scholes algorithm was implemented from C-code with no changes to the source code and achieved a 30X speed-up over processing on a Opteron CPU

Simulation and debugging flows

Fully automated verification flow requiring only the behavioral (untimed test bench written in C/C++/SystemC
AutoPilot takes care of the rest by automatically generating wrappers around the synthesized RTL. The RTL can then be simulated using the original behavioral test bench and stimuli.
Maximal reuse of test bench and test vector eliminates error-prone test bench/vector reconstruction.
Consistent flow for behavioral and RTL SystemC, VHDL, and Verilog RTL models
AutoPilot supports rich set of practical interface protocols such as hand shaking, memory, and FIFO
The AutoPilot simulation and debugging flow is tested and validated with Xilinx and Aldec simulators

What is the learning curve?

AutoPilot has an easy to use Eclipse-based and TCL script user interfaces
No hardware design and synthesis knowledge is necessary
1/2 day of training is recommended to get started

Skill pre-requisite ?

No knowledge of FPGA and hardware design is necessary but is helpful
AutoPilot can be used by both software and hardware designers familiar with high -level languages such as C, C++, SystemC, or M-code
Working knowledge of software centric compilation and debugging environments such as the industry standard Eclipse CDT and/or GNU/make

Suitability and Fit

Who is the target audience?

System architects – writing C, C++, or SystemC for architectural modeling and then using AutoPilot for design space exploration
Software engineers – writing compute-intensive algorithmic and system application software that require hardware acceleration or reconfigurability
System engineers – partitioning and distributing compute-intensive processing on a CPU and FPGA-based processing engines
Hardware engineers – implementing software directly in an FPGA
Verification engineers – fast prototyping and accelerated verification in FPGA hardware

Which applications segments are targeted by this product?

AutoPilot is well suited for multimedia applications such as MPEG4, wireless and communications applications such as forward error correction, networking applications such as encryption and high performance computing applications such as Black-Scholes and Smith-Waterman algorithms.

Main value proposition?

Time to results – delivers the parallel processing resources of an FPGA with significantly less development time and cost – manual RTL coding is eliminated
Ease of use – software design paradigm increases productivity and minimizes development time – 10X reduction in code base size versus RTL; manual RTL recoding eliminated
Maximizes system performance – through memory access, bus communication and interconnect-aware synthesis – 10X-200X performance improvements using FPGAs are now possible
Unifies software and hardware simulation – ability to use a behavioral/architecture-level executable specification throughout the design process

How can you find out if your application is a good candidate for this tool methodology?

The system contains compute-intensive application software functionality that won't run fast enough on a CPU
The application can use the price, performance and power advantages of an FPGA
The design has been described in a high-level language such as C, C++, SystemC, or MATLAB M-code

Language and methodology limitations

AutoPilot has roughly the same language limitations as compiler does for a CPU or DSP
Some constructs are not supported (fileio, some operations/data types for pointers, recursion)
There are no methodology limitations

Successful deployment examples

Success stories to be announced shortly

Customer testimonials

Customer testimonials to be announced shortly

Pricing

AutoPilot's pricing is based on term, perpetual and project license scenarios
Floating and node-locked licenses are supported
Special “Xilinx-only” pricing available
Contact info@autoesl.com for more information

Xilinx Integration

Which Xilinx devices/architectures are supported?

Virtex™-5
Virtex-4
Virtex-II Pro
Virtex-II
Spartan™-3

Which Xilinx CPUs are supported?

PowerPC®
MicroBlaze™

Is the Virtex-4 FX APU supported ?

Contact AutoESL to discuss APU support

Inference of Xilinx Library components

Xilinx slice and DSP elements are automatically used by AutoPilot
Xilinx floating point library is automatically used by AutoPilot
Users can add LogiCORE components to AutoPilot’s library

Benchmark studies targeting Xilinx

C-code for an MPEG4 decoder was synthesized by AutoPilot that achieved the same performance (125 MHz) with a 91 percent smaller code base than the same implementation in RTL (5200 lines of C vs. 57000 lines of VHDL)
A Black-Scholes algorithm was implemented from C-code with no changes to the source code and achieved a 30X speed-up over processing on a Opteron CPU

Flow integration with EDK/XPS, ISE, System Generator (Implementation)

AutoPilot is tested and validated with Xilinx XST logic synthesis tools and Xilinx ISE place-and-route tools

Flow integration with EDK/XPS, ISE, System Generator (Simulation)

Prior to release, the AutoPilot design flow is fully tested with the Xilinx ISE tools
Xilinx ISE tool flow and ModelSim XE/PE for both Verilog and VHDL

Getting Started

How to get started

Contact AutoESL to arrange for an evaluation and training info@autoesl.com

Design examples for various Xilinx boards

AutoPilot has been used to design and implement simple-profile MPEG4 decoder for a Xilinx Virtex-II Pro FPGA development board
AutoPilot has been used to design and implement motion JPEG implementation on a Xilinx XUP development board. Contactinfo@autoesl.com for more information

Info kits available?
(i.e. bundling of boards, software, examples for an integration out of the box experience)