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HLS
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changan2001
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Xilinx AutoESL 做过什么样的设计?
点到为止:JEPG Encoder & decoderMPEG4 SP decoderAESblowfish各种类型的FFT各种类型的FIRtwolameMRCSaberLMSBlockMatchingDQPSK Receiveroptical flowKernelFilterKalmanDUCTurbo Decode原创 2011-10-24 15:12:29 · 1541 阅读 · 8 评论 -
已经有的ESL高层次综合(High Level Synthesis,HLS)产品
AutoPilot from AutoESL ( Xilinx 已经收购AutoESL)BlueSpec Compiler from BlueSpecC-to-Silicon from Cadence Design SystemsSynphony C Compil转载 2011-08-11 12:45:13 · 1305 阅读 · 1 评论 -
BDTI研究认证以DSP为核心的 FPGA设计的高水平综合(HLS)流程
http://china.xilinx.com/china/xcell/xl36/2-7.pdf近年来,高级综合工具已成为在设计方案中使用或希望使用FPGA的工程师的必杀技。这种工具以应用的高级表示法(比如用C语言或MATLAB的M语言编写的表示法)为输入,并生成转载 2011-08-11 13:18:26 · 534 阅读 · 0 评论 -
C to FPGA Who’ll Use the Next Generation of Design Tools?
http://www.eejournal.com/archives/articles/20110621-nextgen/ The von Neumann architecture is a miracle of efficiency if you count转载 2011-08-11 13:09:17 · 552 阅读 · 0 评论 -
FPGA、DSP处理器、C-To-FPGA流程
http://blog.sina.com.cn/s/blog_6018cf350100qkua.html 基于传统手写RTL方法的FPGA设计流程通常会比DSP处理器上用软件实现的同类应用要花费更加多的工作量——这较好地解释了很多DSP处理器用户不愿意改变工作方法转载 2011-08-11 13:07:00 · 889 阅读 · 0 评论 -
常用网站链接
http://www.opengpu.org/forum.php原创 2011-08-11 12:57:04 · 384 阅读 · 2 评论 -
ESL综合之C-to-Verilog 免费工具(新手必看 )
C-to-Verilog is a free on-line C to Verilog compiler. You can copy-and-paste your existing C code and our on-line compiler will synthesize i转载 2011-08-11 12:42:22 · 2339 阅读 · 0 评论 -
AutoESL与Xilinx那些人和事
<br />大年三十,看到Xilinx收购AutoESL的新闻, 顿时觉得今年特别喜庆,于是,连春晚也懒得骂了。 本想立即写一篇博文八卦一番, 怎奈亲朋好友饭局不断,一直拖到今天才动笔。<br />与一年前Xilinx宣布与ARM联姻一样, 这次Xilinx收购AutoESL,堪称影响深远的大事,而这件大事的背后,华人,确切的说,来自中国大陆的精英,是这件大事的绝对主角。他的名字叫丛京生,英文名字 Jason Cong.<br />上照片:<br /><br /><br /> 你如果看Jason的简历,会发转载 2011-04-09 15:47:00 · 1195 阅读 · 0 评论 -
High-level Synthesis from AutoESL: A Game-changer for Chip Design
<br />The theory of natural selection dictates that companies that adapt and change will survive and prosper, while those who don’t will ultimately perish. Chip design is in the midst of a major disruptive change. How can the industry adapt and survive thi转载 2011-04-09 15:45:00 · 652 阅读 · 0 评论 -
C-to-hardware compiler (HLL synthesis)
http://stackoverflow.com/questions/5603285/c-to-hardware-compiler-hll-synthesis7 down vote favorite I try to m转载 2011-08-11 15:45:22 · 704 阅读 · 0 评论 -
NEC推出全球第一个基于C语言的FPGA专用版大规模集成电路设计工具
近日,NEC 推出了半导体设计高阶综合工具CyberWorkBench的FPGA专用版。CyberWorkBench是NEC开发的以C语言为基础的LSI(注1)设计工具。该工具以ANSI-C、SystemC等C语言程序作为输入,以自动生成高性能和高质量的电路的合成工具为中心,具备转载 2011-08-30 10:23:24 · 795 阅读 · 0 评论 -
The future is High-Level Synthesis
The future is high-level synthesis (HLS). As a developer of HLS software, Forte’s vision for this methodology is far reaching and all inclusive, and one we’ve considered for some time. We share a comm转载 2012-03-31 16:26:45 · 628 阅读 · 0 评论 -
High-Level Synthesis with LegUp
LegUp is an open source high-level synthesis tool being developed at the University of Toronto. The LegUp framework allows researchers to improve C to Verilog synthesis without building an infrastruct原创 2011-11-14 10:17:39 · 1480 阅读 · 1 评论 -
推荐初学者从High-Level Synthesis Blue Book开始
High-Level Synthesis Blue Bookby Michael FingeroffAre you an RTL or system designer that is currently using, moving, or planning to move to an HLS design environment?Finally, a comprehensive原创 2011-11-09 13:01:24 · 1944 阅读 · 1 评论 -
Challenges and Opportunities of ESL Design Automation
http://www.eda.org/edps/edp2010/Papers/zhang-chen-ESL.pdf转载 2011-11-09 13:05:18 · 669 阅读 · 0 评论 -
A survey of 1,133 engineers on HLS vs. manual RTL time savings
http://www.deepchip.com/items/0488-04.html From: Shawn McCloud Subject: A survey of 1,133 engineers on HLS vs. manual RTL time savingsHi John,For the third year in a row, Mentor's Catap转载 2011-10-24 14:03:10 · 483 阅读 · 0 评论 -
上海High-level Synthesis Software Engineer(高层次/系统综合软件工程师)
http://www.job9988.com/index/122/p122750.13444339.shtml 少有的机会啊,在国内来说转载 2011-10-24 14:42:30 · 985 阅读 · 3 评论 -
Gary -- "Don't blame Catapult C nor Forte, blame C++ and SystemC"
转载: www.deepchip.com/items/0494-02.html Subject: Gary -- "Don't blame Catapult C nor Forte, blame C++ and SystemC"> C SYNTHESIS IS A KLUDGE> > George Harper's remarks are well observed.转载 2011-10-24 14:01:16 · 606 阅读 · 0 评论 -
Introducing a new high-level synthesis tool called HercuLeS
One of the great things regarding my being the editor of Programmable Logic Designline is that I get to hear about all sorts of cool things. Just a couple of days ago, for example, I received an e转载 2011-10-24 14:22:20 · 816 阅读 · 3 评论 -
Calypto Design Systems Acquires Mentor Catapult C Synthesis Tool
http://finance.yahoo.com/news/Calypto-Design-Systems-iw-3264204374.html?x=0 SANTA CLARA, CA--(Marketwire -08/26/11)- Calypto Design转载 2011-08-29 09:05:13 · 852 阅读 · 1 评论 -
2011: The Year of U.S. High-Level Synthesis Deployment
<br />High-level synthesis has been in production use in Asia for nearly a decade. And, while you’ve been able to buy products from leading Japanese and Korean vendors at your local Best Buy for several years, U.S. companies haven’t widely deployed转载 2011-04-08 13:25:00 · 443 阅读 · 0 评论 -
高层次综合(HLS)熟了
<br />Synopsys收购了synfora, Xilinx收购了AutoESL, Mentor Graphics 有CatapultC<br />种种迹象都表明这些领跑者都在布局高层次综合领域。<br />High level synthesis / C-to-RTL的IC设计时代已经姗姗来迟!原创 2011-03-24 14:41:00 · 2778 阅读 · 3 评论 -
赛灵思宣布收购 AUTOESL
<br />赛灵思宣布收购 AUTOESL<br />支持设计者利用FPGA和可扩展式处理平台提高生产力并加速创新<br />赛灵思公司通过增加高层综合技术扩展了设计方法,把可编程平台的优势带给了<br />更广泛的客户群体<br />2011 年 2 月 1 日,中国北京讯 — 全球可编程平台领导厂商赛灵思公司 (Xilinx, Inc. (NASDAQ:XLNX))宣布收购高层综合技术领先公司美国AutoESL设计科技有限公司。<br />通过增加高层综合技术,赛灵思进一步扩展了其技术基础和产品组合,使转载 2011-02-11 10:45:00 · 2249 阅读 · 2 评论 -
基本运算单元的高层次综合:C/C++ to RTL
本文以加法为例:[code]//----------------------------------------------------//adder.c//---------------------------------------------------void adder(int a, int b, int *sum){ *sum = a + b;}[/code][size=原创 2010-05-26 14:27:00 · 760 阅读 · 0 评论 -
Is it time to start using high-level synthesis?
http://blogs.cancom.com/elogic_920000692/2010/04/30/is-it-time-to-start-using-high-level-synthesis/ One big question people have about high-level synthesis (HLS) is whether or not it is ready fo转载 2010-05-26 15:54:00 · 525 阅读 · 1 评论 -
你还在用HDL语言进行设计吗?
手写RTL的后果是仿真时间长,叠代次数多,bug难寻找,结果就是一个芯片不断的仿真,respin. 业界已经宣称RTL不适宜于大规模的电路设计,很多语言工具不断推出,就是所谓的ESL设计,高级综合,设计语言涉及到systemc,systemverilog,pure c, 类c语言,另类语言. systemc: http://www.bluespec.com ESE http转载 2010-05-26 14:53:00 · 765 阅读 · 0 评论 -
High-level Synthesis Vendors
PICO from SynforaAutoPilot from AutoESLC-to-Silicon from Cadence Design SystemsSynphony HLS from SynopsysPowerOpt from ChipVisionCynthesizer from Forte Design SystemsCatapult C from M原创 2010-05-26 14:44:00 · 831 阅读 · 0 评论 -
VGA(DVI interface) Controller的高层次综合
// Genarate synch signal to drive DVI output, here 720P is as defaultvoid vga_ctrl(volatile int24 *velXY, volatile uint8 *frameY, struct dvi_video *dvi_o, volatile uint1 *sync_enable){ uint12 hcoun原创 2010-05-26 14:28:00 · 488 阅读 · 0 评论 -
实际使用高层次综合(HLS)的时机是否成熟?
人们对高层次综合(HLS)有一个很大的疑问就是它是否已经成为主流使用。换句话说,它是已经主流了还是没有?HLS有历史悠久产品,比如从来没有获得足够重视的Synopsys的行为编译器和Cadence的视觉设计师。然后是下一代产品,Synfora,Forte和Mentor的CatapultC。最近还AutoESL的AutoPilot和Cadence的CtoSilicon。 阿图尔,AutoESL转载 2010-05-26 14:03:00 · 1147 阅读 · 0 评论 -
电子系统级设计(ESL):现实还是涂有外表之物
我经常问的一个问题是:谁在真正使用诸如可以建模的ESL方法,在流程中是否有一些阻碍?另一个通常的问题是:究竟什么是ESL?也许我们应该先说说第二个问题。 对于一些人来说,ESL是指在做任何软硬件部分的决定之前的一个非常高的抽象层次的设计。相比之下,其他人认为ESL是硬件或软件的协同设计。还有一些人会说ESL是优于寄存器传输级(RTL)的更高的抽象层次。当然,我们应该注意到ESL并不一转载 2010-01-18 15:58:00 · 1960 阅读 · 0 评论 -
BDTI unveils FPGA C-synthesis certification: Can C beat RTL?
With the appearance of higher speeds and more DSP macrocells in low-cost FPGAs, more and more design teams are seeing the configurable chips not as glue, but as a way to accelerate the inner loops o转载 2010-01-19 11:41:00 · 487 阅读 · 0 评论 -
ELS电子系统级FPGA设计
电子系统级(ESL)设计是指进化的设计与验证方法,与当前的主流寄存器传送层级(RTL)相比,该方法始于更高级别的提取。 与Verilog与VHDL之类的硬件语言相比,语法与语义中的众多ESL设计语言与流行的ANSI C更为接近。FPGA的ESL工具主要集中在利用软件编程技巧使设计人员能在可编程硬件中轻松实现他们的想法,而无需学习传统的硬件设计技巧。Xilinx 生态系统合作伙伴提供了广转载 2010-01-18 15:44:00 · 1134 阅读 · 0 评论 -
Can C beat RTL?
http://www.edn.com/article/457428-Can_C_beat_RTL_.php With the appearance of higher speeds and more DSP macrocells in low-cost FPGAs, more and more design teams are seeing the configurable chip转载 2010-05-26 14:22:00 · 320 阅读 · 0 评论 -
AutoESL AutoPilot : Customers
CustomersAutoESL’s high level synthesis tool has been adopted by some of the world’s largest software and semi-conductor companies. Our customers have developed products in multiple application do原创 2010-05-26 16:02:00 · 802 阅读 · 0 评论 -
AutoPilot高层次综合C算法设计技巧-移位寄存器
<br /><br />// Register-based shift register implementation using C<br />// for High-Level Synthesis with AutoESL : AutoPilot<br /> <br />#define SIZE 10<br />typedef int dType;<br /> <br />void shiftReg(dType din, dType *dout)<br />{<br />#pragma AUTOPILO原创 2010-06-22 17:43:00 · 777 阅读 · 0 评论 -
Synopsys已经收购synfora
<br />好长时间没去synfora主页溜达了,今天上去看的时候居然redirect到synopsys的主页去了。<br />原来synfora已经被收购。<br /> <br />Synopsys buys Synfora assetsIn its second major acquisition announcement of the day, EDA and IP vendor Synopsys Inc. said Thursday (June 10) it has acquired technol原创 2010-06-21 10:36:00 · 987 阅读 · 0 评论 -
Rumors on Synfora, Forte, CatapultC, AutoESL, CoWare, Calypto, EVE
ESL is definitely the hottest "adjacency" to EDA right now...<br /><br />Take CoWare: Synopsys first bid $50 M for CoWare, then Cadence entered the<br />fray. Eventually Synopsys acquired them for $85 M even though Cadence's bid<br />was higher. Sy转载 2010-06-10 22:37:00 · 855 阅读 · 2 评论 -
The HLS tipping point (引爆点,转折点?)
<br /><br />Jason Cong<br />University of California, Los Angeles<br />Wolfgang Rosenstiel<br />Eberhard Karls Universita¨ t Tu¨bingen<br /> <br />The Tipping Point, by Malcolm Gladwell,defines the tipping point as ‘‘that magic moment when an idea, trend转载 2010-06-10 11:00:00 · 487 阅读 · 0 评论 -
AutoESL at DAC 2010: High-level Synthesis for ASICs and FPGAs
<br />Presentationsby Atrenta, IMEC, National Instruments, Qualcomm, and Xilinx as well asparticipation in a panel on best choice of input language for HLS<br />CUPERTINO, California – June 7, 2010– AutoESL Design Technologies, the technology leader in转载 2010-06-10 00:22:00 · 650 阅读 · 0 评论 -
Wow! Even Microsoft uses AutoESL's C synthesis to speed up its SW
We purchased AutoESL's AutoPilot in 2008 to implement some of the time-<br />consuming cores in our software into FPGA hardware for the runtime speed-up<br />improvements. We found this can often accelerate our SW runtimes by 2-3<br />orders of magn转载 2010-06-10 00:17:00 · 588 阅读 · 0 评论