s3c2440系统时钟

  注：中英文之间不是完全的翻译关系，只是意思相近而已，英文来自于s3c2440的芯片手册。

  s3c2440的时钟控制电路可外接晶振或内部产生。其时钟控制电路为芯片提供三种时钟：FCLK用于CPU核；HCLK用于AHB总线上设备；PCLK用于APB总线上的设备。

  AHB总线主要用于高性能模块（如CPU、DMA和DSP等）之间的连接；APB主要用于低带宽的周边外设之间的连接。

  The Clock control logic in S3C2440A can generate the required clock signals including FCLK for CPU, HCLK for the AHB bus peripherals, and PCLK for the APB bus peripherals.

  s3c2440的最大主频可达400MHZ。但是满足为了降低电磁干扰等要求，CPU外接的时钟频率通常都是很低的。我使用的开发板是JZ2440开发板，所使用的晶振为12MHZ，所以需要通过时钟控制逻辑的PLL提高系统时钟。s3c2440有两个PLL：MPLL和UPLL。UPLL专用于USB设备，MPLL用于设置FCLK、HCLK、PCLK。

  The S3C2440A has two Phase Locked Loops(PLLs): one for FCLK, HCLK, and PCLK, and the other dedicated for USB block (48Mhz).

  MPLL generates the clock to operate MCU at maximum 400Mhz @ 1.3V

  Operating Voltage Range
· Core: 1.20V for 300MHz
           1.30V for 400MHz
  Memory: 1.8V/ 2.5V/3.0V/3.3V
  I/O: 3.3V
  Operating Frequency
· Fclk Up to 400MHz
· Hclk Up to 136MHz
· Pclk Up to 68MHz

从上面这张图看下，提高系统时钟的话，我们需要进行软件的设置：

1. 首先看下系统上电后，待晶振稳定，此时FCLK的时钟大小等于晶振的频率大小，即图中的XTIpll的大小。

2. 当nReset从低电平到高电平，CPU开始执行指令，同时OM[3:2]的电平被内部电路捕获，此时便可以操作PLL了。

3. 启动MPLL，设置寄存器后需要等待一段时间，MPLL输出稳定，LOCKTIME设定Lock Time，Lock Time之后的MPLL输出正常。

Figure shows the clock behavior during the power-on reset sequence. The crystal oscillator begins oscillation within several milliseconds. When nRESET is released after the stabilization of OSC (XTIpll) clock, the PLL starts to operate according to the default PLL configuration. However, PLL is commonly known to be unstable after
power-on reset, so Fin is fed directly to FCLK instead of the Mpll (PLL output) before the software newly configures the PLLCON. Even if the user does not want to change the default value of PLLCON register after reset, the user should write the same value into PLLCON register by software. The PLL restarts the lockup sequence toward the new frequency only after the software configures the PLL with a new frequency. FCLK can be configured as PLL output (Mpll) immediately after lock time.

下面设置系统时钟主要用到四个寄存器：

1. LOCKTIME用于设定设置好寄存器后的等待PLL输出稳定的时间，[31:16]为UPLL，[15:0]为MPLL；

2. MPLLCON寄存器用于设置FCLK与晶振频率的倍数关系，MPLL(FCLK)=(2*m*Fin)/(p*2^s)，m=MDIV+8->[19:12]，p=PDIV+2[9:4]，s=SDIV[1:0]；

The MPLL within the clock generator, as a circuit, synchronizes an output signal with a reference input signal in frequency and phase. In this application, it includes the following basic blocks as shown in Figure 7-2: the Voltage Controlled Oscillator (VCO) to generate the output frequency proportional to input DC voltage, the divider P to
divide the input frequency (Fin) by p, the divider M to divide the VCO output frequency by m which is input to Phase Frequency Detector (PFD), the divider S to divide the VCO output frequency by “s” which is Mpll (the output frequency from MPLL block), the phase difference detector, the charge pump, and the loop filter. The
output clock frequency Mpll is related to the reference input clock frequency Fin by the following equation:

Mpll = (2*m * Fin) / (p * 2s)

m = M (the value for divider M)+ 8, p = P (the value for divider P) + 2.

3. CLKDIVN和CAMDIVN寄存器用于设置FCLK、HCLK和PCLK三者的比例，如下图。

最后说明下：当FCLK不等于HCLK时，即如果HDIVN非0，CPU的总线模式应该从"fast bus mode"向"asynchronous bus mode"转变，通过协处理指令如下：

# MMU_SetAsyncBusMode
mrc p15,0,r0,c1,c0,0
orr r0,r0,#R1_nF:OR:R1_iA
mcr p15,0,r0,c1,c0,0

语句orr r0,r0,#R1_nF:OR:R1_iA是不是看着有点模糊，明显它扯到了协处理器P15的C1寄存器。

  iA位和nF位是控制CPU总线模式的，这里转变为Asynchronous模式，所以C1寄存器的[31：30]为11，所以C1寄存器为0xc0000000。

  mrc p15,0,r0,c1,c0,0
  orr r0,r0,#0xc0000000
  mcr p15,0,r0,c1,c0,0

  如果HDIVN非0时，而CPU的总线模式仍为是"fast bus mode"，则CPU的工作频率将自动变为HCLK，而不是FCLK。

  If HDIVN is not 0 and the CPU bus mode is the fast bus mode, the CPU will operate by the HCLK.
  This feature can be used to change the CPU frequency as a half or more without affecting the HCLK
  and PCLK.

  这个特性可以被用来改变CPU的主频，而不变HCLK和PCLK。