LOCAL STATUS etsecPhyRead
(
VXB_DEVICE_ID pDev,
UINT8 phyAddr,
UINT8 regAddr,
UINT16 *dataVal
)
{
ETSEC_DRV_CTRL * pDrvCtrl;
STATUS rval = ERROR;
FUNCPTR miiRead;
int i;
pDrvCtrl = pDev->pDrvCtrl;
if (CSR_READ_4(pDev, ETSEC_ECNTRL) & ETSEC_ECNTRL_TBIM)
{
if (regAddr == MII_PHY_ID1_REG)
{
*dataVal = TBI_ID1;
return (OK);
}
if (regAddr == MII_PHY_ID2_REG)
{
*dataVal = TBI_ID2;
return (OK);
}
}
else
{
/* Avoid tripping over the TBI management port */
if (phyAddr == pDrvCtrl->etsecTbiAddr)
{
*dataVal = 0xFFFF;
return (ERROR);
}
}
if (phyAddr != pDrvCtrl->etsecMiiPhyAddr && phyAddr < 0x20)
{
*dataVal = 0xFFFF;
return (ERROR);
}
if (phyAddr > 0x1F)
phyAddr -= 32;
/*this is a false phy*/
if(pDrvCtrl->etsecMiiPhyAddr == 0x7){
*dataVal = 0x1234;
return (OK);
}
/*
* If we're not the management device (ETSEC0), then
* forward the read request.
*/
if (pDrvCtrl->etsecMiiDev != pDev && pDrvCtrl->etsecMiiPhyRead != NULL)
{
miiRead = pDrvCtrl->etsecMiiPhyRead;
phyAddr += 32;
return (miiRead (pDrvCtrl->etsecMiiDev, phyAddr, regAddr, dataVal));
}
semTake (pDrvCtrl->etsecDevSem, WAIT_FOREVER);
CSR_WRITE_4(pDev, ETSEC_MIIMADD, regAddr | (phyAddr << 8));
CSR_WRITE_4(pDev, ETSEC_MIIMCOM, 0);
CSR_WRITE_4(pDev, ETSEC_MIIMCOM, ETSEC_MIIMCOM_READ);
for (i = 0; i < ETSEC_TIMEOUT; i++)
{
if ((CSR_READ_4(pDev, ETSEC_MIIMIND) &
(ETSEC_MIIMIND_BUSY|ETSEC_MIIMIND_NOT_VALID)) == 0)
break;
}
if (i == ETSEC_TIMEOUT)
*dataVal = 0xFFFF;
else
{
*dataVal = CSR_READ_4(pDev, ETSEC_MIIMSTAT) & 0xFFFF;
rval = OK;
}
semGive (pDrvCtrl->etsecDevSem);
return (rval);
}
(
VXB_DEVICE_ID pDev,
UINT8 phyAddr,
UINT8 regAddr,
UINT16 *dataVal
)
{
ETSEC_DRV_CTRL * pDrvCtrl;
STATUS rval = ERROR;
FUNCPTR miiRead;
int i;
pDrvCtrl = pDev->pDrvCtrl;
if (CSR_READ_4(pDev, ETSEC_ECNTRL) & ETSEC_ECNTRL_TBIM)
{
if (regAddr == MII_PHY_ID1_REG)
{
*dataVal = TBI_ID1;
return (OK);
}
if (regAddr == MII_PHY_ID2_REG)
{
*dataVal = TBI_ID2;
return (OK);
}
}
else
{
/* Avoid tripping over the TBI management port */
if (phyAddr == pDrvCtrl->etsecTbiAddr)
{
*dataVal = 0xFFFF;
return (ERROR);
}
}
if (phyAddr != pDrvCtrl->etsecMiiPhyAddr && phyAddr < 0x20)
{
*dataVal = 0xFFFF;
return (ERROR);
}
if (phyAddr > 0x1F)
phyAddr -= 32;
/*this is a false phy*/
if(pDrvCtrl->etsecMiiPhyAddr == 0x7){
*dataVal = 0x1234;
return (OK);
}
/*
* If we're not the management device (ETSEC0), then
* forward the read request.
*/
if (pDrvCtrl->etsecMiiDev != pDev && pDrvCtrl->etsecMiiPhyRead != NULL)
{
miiRead = pDrvCtrl->etsecMiiPhyRead;
phyAddr += 32;
return (miiRead (pDrvCtrl->etsecMiiDev, phyAddr, regAddr, dataVal));
}
semTake (pDrvCtrl->etsecDevSem, WAIT_FOREVER);
CSR_WRITE_4(pDev, ETSEC_MIIMADD, regAddr | (phyAddr << 8));
CSR_WRITE_4(pDev, ETSEC_MIIMCOM, 0);
CSR_WRITE_4(pDev, ETSEC_MIIMCOM, ETSEC_MIIMCOM_READ);
for (i = 0; i < ETSEC_TIMEOUT; i++)
{
if ((CSR_READ_4(pDev, ETSEC_MIIMIND) &
(ETSEC_MIIMIND_BUSY|ETSEC_MIIMIND_NOT_VALID)) == 0)
break;
}
if (i == ETSEC_TIMEOUT)
*dataVal = 0xFFFF;
else
{
*dataVal = CSR_READ_4(pDev, ETSEC_MIIMSTAT) & 0xFFFF;
rval = OK;
}
semGive (pDrvCtrl->etsecDevSem);
return (rval);
}