uboot移植之uboot stage1

/*******************************************************************************************************************************************/
u-boot-2009.11
详细步骤参考
mini2440之U-boot移植详细手册-20100419.pdf
嵌入式Linux应用开发完全手册 chapter15
①顶层Makefile添加一个目标依赖命令
mini2440_config : unconfig
    @$(MKCONFIG) $(@:_config=) arm arm920t mini2440 tekkamanninja s3c24x0
并将修改编译器为CROSS_COMPILE ?=arm-linux- (大概line 163)
②对应添加的文件有
uboot/include/configs/mini2440.h (复制相同目录下的sbc2410x.h作为mini2440.h，然后修改)
uboot/board/tekkamanninja/mini2440/ (复制的相同目录下的sbc2410x目录作为mini2440，然后修改)
 ls  mini2440/
 lowlevel_init.S  mini2440.c  nand_read.c    flash.c  .depend      Makefileconfig.mk
③编译步骤是
make mini2440_config
make

/*******************************************************************************************************************************************/
mini2440_config : unconfig
    @$(MKCONFIG) $(@:_config=) arm arm920t mini2440 tekkamanninja s3c24x0
解析此句话：
MKCONFIG=$(SRCTREE)/mkconfig
即源码目录下的mkconfig，mkconfig是一个脚本，后面的arm920t mini2440 tekkamanninja s3c24x0分别是参数，
$2=arm
$3=arm920t 
$4=mini2440 
$5=tekkamanninja 
$6=s3c24x0

mkconfig源码如下：

#!/bin/sh -e

# Script to create header files and links to configure
# U-Boot for a specific board.
#
# Parameters:  Target  Architecture  CPU  Board [VENDOR] [SOC]
#
# (C) 2002-2006 DENX Software Engineering, Wolfgang Denk <wd@denx.de>
#

APPEND=no # Default: Create new config file
BOARD_NAME="" # Name to print in make output


while [ $# -gt 0 ] ; do
case "$1" in
--) shift ; break ;;
-a) shift ; APPEND=yes ;;
-n) shift ; BOARD_NAME="${1%%_config}" ; shift ;;
*)  break ;;
esac
done




[ "${BOARD_NAME}" ] || BOARD_NAME="$1"




[ $# -lt 4 ] && exit 1
[ $# -gt 6 ] && exit 1




echo "Configuring for ${BOARD_NAME} board..."




#
# Create link to architecture specific headers
#
if [ "$SRCTREE" != "$OBJTREE" ] ; then
mkdir -p ${OBJTREE}/include
mkdir -p ${OBJTREE}/include2
cd ${OBJTREE}/include2
rm -f asm//删除asm目录
ln -s ${SRCTREE}/include/asm-$2 asm//根目录下创建asm连接，指向include/asm-arm
LNPREFIX="../../include2/asm/"
cd ../include
rm -rf asm-$2//删除include下的asm-arm
rm -f asm//删除include下的asm
mkdir asm-$2//创建include下的asm-arm
ln -s asm-$2 asm//创建include下的asm链接，指向include/asm-arm
else
cd ./include
rm -f asm
ln -s asm-$2 asm //创建include下的asm，指向include/asm-arm
fi




rm -f asm-$2/arch//删除include/asm-arm下的arch目录




if [ -z "$6" -o "$6" = "NULL" ] ; then
ln -s ${LNPREFIX}arch-$3 asm-$2/arch
else
ln -s ${LNPREFIX}arch-$6 asm-$2/arch
fi




if [ "$2" = "arm" ] ; then
rm -f asm-$2/proc
ln -s ${LNPREFIX}proc-armv asm-$2/proc
fi



//include下创建config.mk
#
# Create include file for Make
#
echo "ARCH   = $2" >  config.mk
echo "CPU    = $3" >> config.mk
echo "BOARD  = $4" >> config.mk

[ "$5" ] && [ "$5" != "NULL" ] && echo "VENDOR = $5" >> config.mk

[ "$6" ] && [ "$6" != "NULL" ] && echo "SOC    = $6" >> config.mk


//include下创建config.h
#
# Create board specific header file
#
if [ "$APPEND" = "yes" ] # Append to existing config file
then
echo >> config.h
else
> config.h # Create new config file
fi
echo "/* Automatically generated - do not edit */" >>config.h
echo "#include <configs/$1.h>" >>config.h //configs/
echo "#include <asm/config.h>" >>config.h


exit 0

mkconfig这个脚本程序实际上就为我们生成了两个文件，一个是include/config.h，另一个是include/config.mk.

我们可以在make smdk2410_config之前看一下include下面是没有这两个文件的。config.h里面只有一句话：

/* Automatically generated - do not edit */
        #include <config/smdk2410.h>

其实就是为我们包含了目标平台的配置头文件。另一个文件config.mk里面则有如下内容：

ARCH = arm
        CPU = arm920t
        BOARD = smdk2410
        SOC = s3c24x0

其实这里面定义了四个变量，分别是体系结构（arm）、处理器核（arm920t）、目标板（smdk2410）、片上系统（s3c24x0）。

refer to http://www.embedu.org/Column/Column291.htm

/*******************************************************************************************************************************************/
首先要知道Steppingstone是什么东东，s3c2440 spec上关于4kB Steppingstone的介绍
S3C2440A boot code can be executed on an external NAND flash memory. In order to support NAND flash boot
loader, the S3C2440A is equipped with an internal SRAM buffer called ‘Steppingstone’. When booting, the first 4
KBytes of the NAND flash memory will be loaded into Steppingstone and the boot code loaded into Steppingstone
will be executed
S3C2440A支持从nand启动，所付出的代价是在内部增加4KB SRAM，即所谓的Steppingstone ，恩，要是增加512KB的sram就好了，就不必把uboot考来考去了
1.当板子打到nand侧，即将om0脚接地。打开电源，cpu启动时会检测到，将4KB Steppingstone映射到地址0-FFFF， 然后由硬件自动将nandflash的前4KB(存放着uboot)考到起始地址为0处，cpu从0地址开始执行
2.这4KB代码的主要任务是将uboot的 其他代码(其实默认是uboot的全部代码,从传递给nand_read_ll的参数可知)考到sdram的一个合适位置处，和设置cpu最基本的寄存器
从uboot/cpu/arm920t/u-boot.lds的链接控制脚本(可参考链接装载和库 p130)可以看出，希望start.S  lowlevel_init.S nand_read.c这三个文件在4KB的Steppingstone 中执行，由他们拷贝uboot代码和...

	. = 0x00000000;
	. = ALIGN(4);
	.text :
	{
		cpu/arm920t/start.o	(.text)
		board/tekkamanninja/mini2440/lowlevel_init.o (.text)
		board/tekkamanninja/mini2440/nand_read.o (.text)
		*(.text)
	}

在start.S中，
首先要对cpu频率初始化设置，FCLK

/*
 *  armboot - Startup Code for ARM920 CPU-core
 *
 *  Copyright (c) 2001	Marius Gröger <mag@sysgo.de>
 *  Copyright (c) 2002	Alex Züpke <azu@sysgo.de>
 *  Copyright (c) 2002	Gary Jennejohn <garyj@denx.de>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <config.h>

/*
 *************************************************************************
 *
 * Jump vector table as in table 3.1 in [1]
 *
 *************************************************************************
 */


.globl _start
/*
.globl gnu asm伪指令，将_start定义为全局标号
gnu ams伪指令参考http://blog.sina.com.cn/s/blog_574d08530100hzie.html
*/
_start:	b	start_code//b arm asm跳转指令，跳转到标号start_code处
	ldr	pc, _undefined_instruction//ldr arm asm存储器访问指令，加载标号_undefined_instruction所表示地址处的内容到pc
	ldr	pc, _software_interrupt
	ldr	pc, _prefetch_abort
	ldr	pc, _data_abort
	ldr	pc, _not_used
	ldr	pc, _irq
	ldr	pc, _fiq

_undefined_instruction:	.word undefined_instruction
/*
.word gnu asm汇编伪指令，分配一段字内存单元，并用undefined_instruction(即此标号表示的地址值)初始化字内存单元(32bit)
此行的效果是在_undefined_instruction位置处存储了32位内存，其内容是undefined_instruction的地址值
undefined_instruction一个在后面定义的标号，
参考帖子http://www.linuxforum.net/forum/showflat.php?Cat=&Board=linuxK&Number=563178
*/
_software_interrupt:	.word software_interrupt
_prefetch_abort:	.word prefetch_abort
_data_abort:		.word data_abort
_not_used:		.word not_used
_irq:			.word irq
_fiq:			.word fiq

	.balignl 16,0xdeadbeef
/*
从后面的反汇编代码
  3c:    deadbeef     .word    0xdeadbeef
  40:    33f80000     .word    0x33f80000
可以看出从地址3c至3f这4字节的数据是0xdeadbeef，作为检测nand or nor启动的手段
检测时，会向地址0x40000003c写入32个0，然后去读地址0x3c看是否为0，是0则判断为nand启动。详见CHECK_BOOT_FLASH那段
参考
http://blog.chinaunix.net/space.php?uid=20543672&do=blog&cuid=2085212
http://zqwt.012.blog.163.com/blog/static/12044684201031102956976/
*/

/*
 *************************************************************************
 *
 * Startup Code (called from the ARM reset exception vector)
 *
 * do important init only if we don't start from memory!
 * relocate armboot to ram
 * setup stack
 * jump to second stage
 *
 *************************************************************************
 */

_TEXT_BASE://标号
	.word	TEXT_BASE

.globl _armboot_start
_armboot_start:
	.word _start

/*
 * These are defined in the board-specific linker script.
 */
.globl _bss_start
_bss_start:
	.word __bss_start

.globl _bss_end
_bss_end:
	.word _end

#ifdef CONFIG_USE_IRQ
/* IRQ stack memory (calculated at run-time) */
.globl IRQ_STACK_START
IRQ_STACK_START:
	.word	0x0badc0de

/* IRQ stack memory (calculated at run-time) */
.globl FIQ_STACK_START
FIQ_STACK_START:
	.word 0x0badc0de
#endif


/*
 * the actual start code
 */

start_code:
	/*
	 * set the cpu to SVC32 mode
	 */
	mrs	r0, cpsr//mrs读状态寄存器指令，到r0
	bic	r0, r0, #0x1f//bic位清除指令，r0 <- r0&~0x1f，最后5位清零
	orr	r0, r0, #0xd3//orr逻辑或指令，最后5位是10011，即supervisor模式
	msr	cpsr, r0//msr写状态寄存器指令，从r0

//	bl	coloured_LED_init
//	bl	red_LED_on

#if	defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK)//#if arm asm伪指令，控制是否汇编对应内容
	/*
	 * relocate exception table
	 */
	ldr	r0, =_start//此处ldr是arm asm伪指令，大范围地址读取(第二个操作数前有=号),读标号_start地址到r0
	ldr	r1, =0x0//仍是arm asm伪指令，(第二个操作数前有=号),读0到r1
	mov	r2, #16//向r2写入16
copyex:
	subs	r2, r2, #1//sub减法指令,s表示结果影响cpsr的值，r2 <- r2-1
 	ldr	r3, [r0], #4//ldr指定内存地址上的数据到寄存器中，和str相对，r3 <- [addr]
	str	r3, [r1], #4//str存储寄存器数据到内存地址中，r3 -> [addr]
	bne	copyex//b跳转，ne条件，即不相等跳转
#endif
/*
和 指令ldr( ldr r0,[r1] 加载内存地址r1处数据到寄存器r0)易混的几个指令
1.str指令，和指令ldr方向相反，str r0,[r1] 存储寄存器r0数据到r1指定的内存地址里
2.ldr伪指令，和指令str名称相同但用法不同，ldr r0,=xx，加载标号地址或者加载立即数到r0
3.adr伪指令，其实他和ldr伪指令是一类，都是加载标号地址到寄存器，但不用加=号(ldr伪指令加=号是为了和ldr指令区分),如adr    r0, _start加载标号_start地址到r0
但是adr加载的标号是相对地址所以是地址无关的，即不管当前代码段的基地址在什么位置，用adr r0,_start总能获得_start准确的地址值,
ldr r0 =_start 是加载_start的绝对地址到r0,_start的绝对地址是再链接时已经确定，所以如果_start代码如果在运行期间重新被搬到另一个内存区域中，那么_start的地址
肯定和链接时的不一样了，所以这种情况下不能用ldr伪指令，而adr貌似就是为这种情况准备的
adr
*/
#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410)|| defined(CONFIG_S3C2440)
	/* turn off the watchdog */

# if defined(CONFIG_S3C2400)
#  define pWTCON	0x15300000
#  define INTMSK	0x14400008	/* Interupt-Controller base addresses */
#  define CLKDIVN	0x14800014	/* clock divisor register */
#else
#  define pWTCON	0x53000000
#  define INTMSK	0x4A000008	/* Interupt-Controller base addresses */
#  define INTSUBMSK	0x4A00001C
#  define CLKDIVN	0x4C000014	/* clock divisor register */
# endif

#define CLK_CTL_BASE	0x4C000000	/* tekkaman */
#define MDIV_405	0x7f << 12	/* tekkaman */
#define PSDIV_405	0x21		/* tekkaman */
#define MDIV_200	0xa1 << 12	/* tekkaman */
#define PSDIV_200	0x31		/* tekkaman */

	ldr	r0, =pWTCON
	mov	r1, #0x0
	str	r1, [r0]

	/*
	 * mask all IRQs by setting all bits in the INTMR - default
	 */
	mov	r1, #0xffffffff
	ldr	r0, =INTMSK
	str	r1, [r0]
# if defined(CONFIG_S3C2410)
	ldr	r1, =0x7ff
	ldr	r0, =INTSUBMSK
	str	r1, [r0]
# endif


#if defined(CONFIG_S3C2440)
	ldr	r1, =0x7fff	
	ldr	r0, =INTSUBMSK
	str	r1, [r0]
#endif

#if defined(CONFIG_S3C2440)
	/* FCLK:HCLK:PCLK = 1:4:8 */
	ldr	r0, =CLKDIVN
	mov	r1, #5
	str	r1, [r0]
	
	mrc	p15, 0, r1, c1, c0, 0	
	orr	r1, r1, #0xc0000000		
	mcr	p15, 0, r1, c1, c0, 0	
	
	
	mov	r1, #CLK_CTL_BASE	
	mov	r2, #MDIV_405	
	add	r2, r2, #PSDIV_405	
	str	r2, [r1, #0x04]		/* MPLLCON tekkaman */
#else

	/* FCLK:HCLK:PCLK = 1:2:4 */
	/* default FCLK is 120 MHz ! */
	ldr	r0, =CLKDIVN
	mov	r1, #3
	str	r1, [r0]
//#endif	/* CONFIG_S3C2400 || CONFIG_S3C2410 */
	mrc	p15, 0, r1, c1, c0, 0	
	orr	r1, r1, #0xc0000000	
	mcr	p15, 0, r1, c1, c0, 0	/*write ctrl register tekkaman*/
	
	
	mov	r1, #CLK_CTL_BASE	/* tekkaman*/
	mov	r2, #MDIV_200	
	add	r2, r2, #PSDIV_200	
	str	r2, [r1, #0x04]
#endif
#endif	/* CONFIG_S3C2400 || CONFIG_S3C2410  || CONFIG_S3C2440*/

	/*
	 * we do sys-critical inits only at reboot,
	 * not when booting from ram!
	 */
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
	bl	cpu_init_crit
#endif

//#ifndef CONFIG_SKIP_RELOCATE_UBOOT
//relocate:				/* relocate U-Boot to RAM	    */
/***************** CHECK_CODE_POSITION ******************************************/
	adr	r0, _start		
/*  
将标号_start的地址给r0
此处获得的标号_start的地址值
可能是0，表示代码还运行在norflash中(从nor启动)或Steppingstone中(从nand启动)
可能是0x33f80000,表示代码已运行在sdram中
须用adr指令，不可以用ldr r0,=_start,因为_start=0,这在链接时已经确定
而adr r0,_start伪指令会自动翻译成这样的指令:用当前pc值加上或减去pc至_start和偏移值给r0,所以r就0取得了当前代码中标号_start的真实地址

 */
	ldr	r1, _TEXT_BASE		
/* 
加载标号_TEXT_BASE地址处的内容到r1,而标号_TEXT_BASE处的内容是0x33f80000，表示uboot加载到sdram的起始位置而起始位置处是_start标号，用上面取得
的_start标号地址此_start标号地址0x33f80000和比较,(相等,处于在sdram;不等,处于norflash或Steppingstone)
 */
	cmp	r0, r1			
/*   
比较
*/
	beq	stack_setup
/*
相等，说明uboot已在sdram,不必执行下面搬运代码了，跳到stack_setup为第二阶段的c代码准备堆栈
不等，先判断是nand启动还是nor启动

有个疑问哦，uboot在启动时或者从nand或者从nor,不管哪种情况都需要执行搬运代码到sdram,既然是uboot自己搬运的，uboot肯定知道自己做了什么，为什么还要去检查身处
何处呢?答：uboot除了从nand和nor启动还有另外一种情况，就是可以用调试器将uboot直接下载到sdramd运行，此时uboot整体都在sdram上了，当然不必执行自搬运了
这段代码就是为了兼容这种情况而加入的
我想在用调试器下载uboot时，应该下载到0x3ff8000处，和TEXT_BASE要对应，否则uboot还会执行搬运
*/
/***************** CHECK_CODE_POSITION ******************************************/

/***************** CHECK_BOOT_FLASH ******************************************/
	ldr	r1, =( (4<<28)|(3<<4)|(3<<2) )		
/* address of Internal SRAM  0x4000003C， 读取地址0x40000003c的内容到r1
为什么是3c？可以看后面的反汇编代码，地址3c处预放置了一个数字，0xdeadbeef
 */
	mov	r0, #0		/* r0 = 0 */
	str	r0, [r1]        /*存储寄存器r0数据0到内存单元0x4000003c*/


	mov	r1, #0x3c		/* address of men  0x0000003C*/
	ldr	r0, [r1]        /*加载内存单元0x3c内容到r0寄存器*/
	cmp	r0, #0          /*看是否为0*/
	bne	relocate        /*不等说明是，nor启动，跳到relocate； 相等，nand 启动，继续执行*/
//即过程是：清零0x4000003c单元，再读取0x3c单元，如果读到是0,说明nand启动,否则为nor启动
//至于检测原理，参考http://blog.chinaunix.net/space.php?uid=20543672&do=blog&cuid=2085212

	/* recovery  */
	ldr	r0, =(0xdeadbeef)//加载立即数0xdeadbeef到r0
	ldr	r1, =( (4<<28)|(3<<4)|(3<<2) )
	str	r0, [r1]//将r0写入内存0x4000003c
/***************** CHECK_BOOT_FLASH ******************************************/

/***************** NAND_BOOT *************************************************/

#define LENGTH_UBOOT 0x60000
#define NAND_CTL_BASE 0x4E000000

#ifdef CONFIG_S3C2440
/* Offset */
#define oNFCONF 0x00
#define oNFCONT 0x04
#define oNFCMD 0x08
#define oNFSTAT 0x20

	@ reset NAND
	mov	r1, #NAND_CTL_BASE
	ldr	r2, =( (7<<12)|(7<<8)|(7<<4)|(0<<0) )
	str	r2, [r1, #oNFCONF]
	ldr	r2, [r1, #oNFCONF]
	
	ldr	r2, =( (1<<4)|(0<<1)|(1<<0) )	@ Active low CE Control 
	str	r2, [r1, #oNFCONT]
	ldr	r2, [r1, #oNFCONT]
	
	ldr	r2, =(0x6)	@ RnB Clear
	str	r2, [r1, #oNFSTAT]
	ldr	r2, [r1, #oNFSTAT]
	
	mov	r2, #0xff	@ RESET command
	strb	r2, [r1, #oNFCMD]
	
	mov	r3, #0	@ wait
nand1: 
	add	r3, r3, #0x1
	cmp	r3, #0xa
	blt	nand1

nand2:
	ldr	r2, [r1, #oNFSTAT]	@ wait ready
	tst	r2, #0x4
	beq	nand2
	
	
	ldr	r2, [r1, #oNFCONT]
	orr	r2, r2, #0x2	@ Flash Memory Chip Disable
	str	r2, [r1, #oNFCONT]
	
	@ get read to call C functions (for nand_read())
	ldr	sp, DW_STACK_START	@ setup stack pointer
	mov	fp, #0	@ no previous frame, so fp=0

	@ copy U-Boot to RAM
	ldr	r0, =TEXT_BASE//第一个参数，指定要放在sdram的哪个起始地址，在/board/tekkamanninja/mini2440/config.mk中定义TEXT_BASE = 0x33F80000
	mov	r1, #0x0//第二个参数，指定从nandflash的哪个起始地址，默认为0，说明拷贝的是整个uboot
	mov	r2, #LENGTH_UBOOT//拷贝的长度，在本文件定义，#define LENGTH_UBOOT 0x60000
	bl	nand_read_ll/********************************************************call nand_read_ll*************************************/
	tst	r0, #0x0
	beq	ok_nand_read

bad_nand_read:
loop2:
	b	loop2	@ infinite loop
ok_nand_read:
	@ verify
	mov	r0, #0
	ldr	r1, =TEXT_BASE
	mov	r2, #0x400	@ 4 bytes * 1024 = 4K-bytes
go_next:
	ldr	r3, [r0], #4
	ldr	r4, [r1], #4
	teq	r3, r4
	bne	notmatch
	subs	r2, r2, #4
	beq	stack_setup
	bne	go_next

notmatch:
loop3:
	b	loop3	@ infinite loop
#endif

#ifdef	CONFIG_S3C2410

/* Offset */
#define oNFCONF 0x00
#define oNFCMD 0x04
#define oNFSTAT 0x10

	@ reset NAND
	mov	r1, #NAND_CTL_BASE
	ldr	r2, =0xf830	@ initial value
	str	r2, [r1, #oNFCONF]
	ldr	r2, [r1, #oNFCONF]
	bic	r2, r2, #0x800	@ enable chip
	str	r2, [r1, #oNFCONF]
	mov	r2, #0xff		@ RESET command
	strb	r2, [r1, #oNFCMD]
	
	
	mov	r3, #0	@ wait
nand1:
	add	r3, r3, #0x1
	cmp	r3, #0xa
	blt	nand1

nand2:
	ldr	r2, [r1, #oNFSTAT]	@ wait ready
	tst	r2, #0x1
	beq	nand2
	
	ldr	r2, [r1, #oNFCONF]
	orr	r2, r2, #0x800	@ disable chip
	str	r2, [r1, #oNFCONF]
	
	@ get read to call C functions (for nand_read())
	ldr	sp, DW_STACK_START	@ setup stack pointer
	mov	fp, #0	@ no previous frame, so fp=0
	
	@ copy U-Boot to RAM
	ldr	r0, =TEXT_BASE
	mov	r1, #0x0
	mov	r2, #LENGTH_UBOOT
	bl	nand_read_ll
	tst	r0, #0x0
	beq	ok_nand_read

bad_nand_read:
loop2:
	b	loop2	@ infinite loop


ok_nand_read:
	@ verify
	mov	r0, #0
	ldr	r1, =TEXT_BASE
	mov	r2, #0x400	@ 4 bytes * 1024 = 4K-bytes
go_next:
	ldr	r3, [r0], #4
	ldr	r4, [r1], #4
	teq	r3, r4
	bne	notmatch
	subs	r2, r2, #4
	beq	stack_setup
	bne	go_next

notmatch:
loop3:
	b	loop3	@ infinite loop

#endif
/***************** NAND_BOOT *************************************************/

/***************** NOR_BOOT *************************************************/
relocate:				/* relocate U-Boot to RAM	    */
      /*********** CHECK_FOR_MAGIC_NUMBER***************/
	ldr	r1, =(0xdeadbeef)
	cmp	r0, r1//确认内存单元0x3c内容是否是0xdeadbeef
	bne	loop3//不等，说明nor flash中的uboot数据有误，去死循环；相等继续执行
      /*********** CHECK_FOR_MAGIC_NUMBER***************/
	adr	r0, _start		/* r0=起始源地址，_start=0   */
	ldr	r1, _TEXT_BASE		/* r1=起始目标地址，_TEXT_BASE=0xff380000*/
	ldr	r2, _armboot_start     /*r2=代码段起始地址*/
	ldr	r3, _bss_start         /*r3=代码段结束地址*/
	sub	r2, r3, r2		/* r2 =代码段长度 */
	add	r2, r0, r2		/* r2 =代码段结束地址        */

copy_loop://开始从norflash的0地址拷贝数据即uboot代码段 到sdram的0x3ff80000开始处
	ldmia	r0!, {r3-r10}		
/* copy from source address [r0]   
ldm 加载基址寄存器r0指向的地址上的数据到r3,r4,r5,r6,r7,r8,r9,r10寄存器组；ia 每次传输后r0 <- r0+4；！指示用最后的地址更新基址寄存器(此处为r0)的内容
 */
	stmia	r1!, {r3-r10}		
/* copy to   target address [r1]   
stm 将寄存器列表的数据存储到基址寄存器(此处为r1)所指向的地址；同上，基址寄存器(此处为r1)的内容也会更新
 */
	cmp	r0, r2			
/* until source end addreee [r2]   
r0开始=_start，没拷贝一次数据，+4
r2=代码段结束地址
 */
	ble	copy_loop
/***************** NOR_BOOT *************************************************/

	/* Set up the stack						    */
stack_setup:
	ldr	r0, _TEXT_BASE		/* upper 128 KiB: relocated uboot   */
	sub	r0, r0, #CONFIG_SYS_MALLOC_LEN	/* malloc area              */
	sub	r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo                 */
#ifdef CONFIG_USE_IRQ
	sub	r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
#endif
	sub	sp, r0, #12		/* leave 3 words for abort-stack    */

clear_bss:
	ldr	r0, _bss_start		/* find start of bss segment        */
	ldr	r1, _bss_end		/* stop here                        */
	mov	r2, #0x00000000		/* clear                            */

clbss_l:str	r2, [r0]		/* clear loop...                    */
	add	r0, r0, #4
	cmp	r0, r1
	ble	clbss_l

	ldr	pc, _start_armboot
//#define CONFIG_MINI2440_LED 1
#if defined(CONFIG_MINI2440_LED)
#define GPIO_CTL_BASE 0x56000000
#define oGPIO_B 0x10
#define oGPIO_CON 0x0
/* R/W, Configures the pins of the port */
#define oGPIO_DAT 0x4
#define oGPIO_UP 0x8
/* R/W, Pull-up disable register */
	mov	r1, #GPIO_CTL_BASE
	add	r1, r1, #oGPIO_B
	ldr	r2, =0x295551
	str	r2, [r1, #oGPIO_CON]
	mov	r2, #0xff
	str	r2, [r1, #oGPIO_UP]
	ldr	r2, =0x1c1
	str	r2, [r1, #oGPIO_DAT]
#endif

_start_armboot:	.word start_armboot
#define STACK_BASE 0x33f00000
#define STACK_SIZE 0x10000
	.align	2
DW_STACK_START:	.word	STACK_BASE+STACK_SIZE-4 
/*
 *************************************************************************
 *
 * CPU_init_critical registers
 *
 * setup important registers
 * setup memory timing
 *
 *************************************************************************
 */


#ifndef CONFIG_SKIP_LOWLEVEL_INIT
cpu_init_crit:
	/*
	 * flush v4 I/D caches
	 */
	mov	r0, #0
	mcr	p15, 0, r0, c7, c7, 0	/* flush v3/v4 cache */
	mcr	p15, 0, r0, c8, c7, 0	/* flush v4 TLB */

	/*
	 * disable MMU stuff and caches
	 */
	mrc	p15, 0, r0, c1, c0, 0
	bic	r0, r0, #0x00002300	@ clear bits 13, 9:8 (--V- --RS)
	bic	r0, r0, #0x00000087	@ clear bits 7, 2:0 (B--- -CAM)
	orr	r0, r0, #0x00000002	@ set bit 2 (A) Align
	orr	r0, r0, #0x00001000	@ set bit 12 (I) I-Cache
	mcr	p15, 0, r0, c1, c0, 0

	/*
	 * before relocating, we have to setup RAM timing
	 * because memory timing is board-dependend, you will
	 * find a lowlevel_init.S in your board directory.
	 */
	mov	ip, lr

	bl	lowlevel_init/***********************************************************call lowlevel_init******************************/

	mov	lr, ip
	mov	pc, lr
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */

/*
 *************************************************************************
 *
 * Interrupt handling
 *
 *************************************************************************
 */

@
@ IRQ stack frame.
@
#define S_FRAME_SIZE	72

#define S_OLD_R0	68
#define S_PSR		64
#define S_PC		60
#define S_LR		56
#define S_SP		52

#define S_IP		48
#define S_FP		44
#define S_R10		40
#define S_R9		36
#define S_R8		32
#define S_R7		28
#define S_R6		24
#define S_R5		20
#define S_R4		16
#define S_R3		12
#define S_R2		8
#define S_R1		4
#define S_R0		0

#define MODE_SVC	0x13
#define I_BIT		0x80

/*
 * use bad_save_user_regs for abort/prefetch/undef/swi ...
 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
 */

	.macro	bad_save_user_regs
	sub	sp, sp, #S_FRAME_SIZE
	stmia	sp, {r0 - r12}			@ Calling r0-r12
	ldr	r2, _armboot_start
	sub	r2, r2, #(CONFIG_STACKSIZE)
	sub	r2, r2, #(CONFIG_SYS_MALLOC_LEN)
	/* set base 2 words into abort stack */
	sub	r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8)
	ldmia	r2, {r2 - r3}			@ get pc, cpsr
	add	r0, sp, #S_FRAME_SIZE		@ restore sp_SVC

	add	r5, sp, #S_SP
	mov	r1, lr
	stmia	r5, {r0 - r3}			@ save sp_SVC, lr_SVC, pc, cpsr
	mov	r0, sp
	.endm

	.macro	irq_save_user_regs
	sub	sp, sp, #S_FRAME_SIZE
	stmia	sp, {r0 - r12}			@ Calling r0-r12
	add	r7, sp, #S_PC
	stmdb	r7, {sp, lr}^			@ Calling SP, LR
	str	lr, [r7, #0]			@ Save calling PC
	mrs	r6, spsr
	str	r6, [r7, #4]			@ Save CPSR
	str	r0, [r7, #8]			@ Save OLD_R0
	mov	r0, sp
	.endm

	.macro	irq_restore_user_regs
	ldmia	sp, {r0 - lr}^			@ Calling r0 - lr
	mov	r0, r0
	ldr	lr, [sp, #S_PC]			@ Get PC
	add	sp, sp, #S_FRAME_SIZE
	/* return & move spsr_svc into cpsr */
	subs	pc, lr, #4
	.endm

	.macro get_bad_stack
	ldr	r13, _armboot_start		@ setup our mode stack
	sub	r13, r13, #(CONFIG_STACKSIZE)
	sub	r13, r13, #(CONFIG_SYS_MALLOC_LEN)
	/* reserve a couple spots in abort stack */
	sub	r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8)

	str	lr, [r13]			@ save caller lr / spsr
	mrs	lr, spsr
	str	lr, [r13, #4]

	mov	r13, #MODE_SVC			@ prepare SVC-Mode
	@ msr	spsr_c, r13
	msr	spsr, r13
	mov	lr, pc
	movs	pc, lr
	.endm

	.macro get_irq_stack			@ setup IRQ stack
	ldr	sp, IRQ_STACK_START
	.endm

	.macro get_fiq_stack			@ setup FIQ stack
	ldr	sp, FIQ_STACK_START
	.endm

/*
 * exception handlers
 */
	.align  5
undefined_instruction:
	get_bad_stack
	bad_save_user_regs
	bl	do_undefined_instruction

	.align	5
software_interrupt:
	get_bad_stack
	bad_save_user_regs
	bl	do_software_interrupt

	.align	5
prefetch_abort:
	get_bad_stack
	bad_save_user_regs
	bl	do_prefetch_abort

	.align	5
data_abort:
	get_bad_stack
	bad_save_user_regs
	bl	do_data_abort

	.align	5
not_used:
	get_bad_stack
	bad_save_user_regs
	bl	do_not_used

#ifdef CONFIG_USE_IRQ

	.align	5
irq:
	get_irq_stack
	irq_save_user_regs
	bl	do_irq
	irq_restore_user_regs

	.align	5
fiq:
	get_fiq_stack
	/* someone ought to write a more effiction fiq_save_user_regs */
	irq_save_user_regs
	bl	do_fiq
	irq_restore_user_regs

#else

	.align	5
irq:
	get_bad_stack
	bad_save_user_regs
	bl	do_irq

	.align	5
fiq:
	get_bad_stack
	bad_save_user_regs
	bl	do_fiq

#endif

关于判断nand和nor的问题，有个疑问
http://blog.csdn.net/zhaocj/article/details/5803699
http://blog.chinaunix.net/space.php?uid=20543672&do=blog&cuid=2085212

Tekkaman Ninja是对地址0和地址0x40000000进行处理而判断是从nand或nor启动的
zhaocj是对 BWSCON寄存器，对应nand nor拨码开关，的检测而判断从哪启动
我感觉后者不是更简便吗，所以应该可以用后者的，可参考下面这个博客
http://blog.chinaunix.net/space.php?uid=22337711&do=blog&id=1774867

总结一下流程

其中，stack_setup是给stage2的c代码设置堆栈空间，就是将sp指向一个空白的内存单元即可
设置完堆栈，即转到第二阶段的入口，在line 503
 ldr pc, _start_armboot
start_armboot 在uboot/lib_arm/board.c中，下篇给出board.c的源码
如下是start.S的反汇编

cpu/arm920t/start.o:     file format elf32-littlearm


Disassembly of section .text:

00000000 <_start>:
 *************************************************************************
 */


.globl _start
_start:	b	start_code
   0:	ea000012 	b	50 <start_code>
	ldr	pc, _undefined_instruction
   4:	e59ff014 	ldr	pc, [pc, #20]	; 20 <_undefined_instruction>
	ldr	pc, _software_interrupt
   8:	e59ff014 	ldr	pc, [pc, #20]	; 24 <_software_interrupt>
	ldr	pc, _prefetch_abort
   c:	e59ff014 	ldr	pc, [pc, #20]	; 28 <_prefetch_abort>
	ldr	pc, _data_abort
  10:	e59ff014 	ldr	pc, [pc, #20]	; 2c <_data_abort>
	ldr	pc, _not_used
  14:	e59ff014 	ldr	pc, [pc, #20]	; 30 <_not_used>
	ldr	pc, _irq
  18:	e59ff014 	ldr	pc, [pc, #20]	; 34 <_irq>
	ldr	pc, _fiq
  1c:	e59ff014 	ldr	pc, [pc, #20]	; 38 <_fiq>

00000020 <_undefined_instruction>:
  20:	00000240 	.word	0x00000240

00000024 <_software_interrupt>:
  24:	000002a0 	.word	0x000002a0

00000028 <_prefetch_abort>:
  28:	00000300 	.word	0x00000300

0000002c <_data_abort>:
  2c:	00000360 	.word	0x00000360

00000030 <_not_used>:
  30:	000003c0 	.word	0x000003c0

00000034 <_irq>:
  34:	00000420 	.word	0x00000420

00000038 <_fiq>:
  38:	00000480 	.word	0x00000480
  3c:	deadbeef 	.word	0xdeadbeef

00000040 <_TEXT_BASE>:
  40:	33f80000 	.word	0x33f80000

00000044 <_armboot_start>:
  44:	00000000 	.word	0x00000000

00000048 <_bss_start>:
  48:	00000000 	.word	0x00000000

0000004c <_bss_end>:
  4c:	00000000 	.word	0x00000000

00000050 <start_code>:

start_code:
	/*
	 * set the cpu to SVC32 mode
	 */
	mrs	r0, cpsr
  50:	e10f0000 	mrs	r0, CPSR
	bic	r0, r0, #0x1f
  54:	e3c0001f 	bic	r0, r0, #31
	orr	r0, r0, #0xd3
  58:	e38000d3 	orr	r0, r0, #211	; 0xd3
	msr	cpsr, r0
  5c:	e129f000 	msr	CPSR_fc, r0
#define MDIV_405	0x7f << 12	/* tekkaman */
#define PSDIV_405	0x21		/* tekkaman */
#define MDIV_200	0xa1 << 12	/* tekkaman */
#define PSDIV_200	0x31		/* tekkaman */

	ldr	r0, =pWTCON
  60:	e3a00453 	mov	r0, #1392508928	; 0x53000000
	mov	r1, #0x0
  64:	e3a01000 	mov	r1, #0
	str	r1, [r0]
  68:	e5801000 	str	r1, [r0]

	/*
	 * mask all IRQs by setting all bits in the INTMR - default
	 */
	mov	r1, #0xffffffff
  6c:	e3e01000 	mvn	r1, #0
	ldr	r0, =INTMSK
  70:	e59f0468 	ldr	r0, [pc, #1128]	; 4e0 <fiq+0x60>
	str	r1, [r0]
  74:	e5801000 	str	r1, [r0]
# if defined(CONFIG_S3C2410)
	ldr	r1, =0x7ff
  78:	e59f1464 	ldr	r1, [pc, #1124]	; 4e4 <fiq+0x64>
	ldr	r0, =INTSUBMSK
  7c:	e59f0464 	ldr	r0, [pc, #1124]	; 4e8 <fiq+0x68>
	str	r1, [r0]
  80:	e5801000 	str	r1, [r0]
	str	r2, [r1, #0x04]		/* MPLLCON tekkaman */
#else

	/* FCLK:HCLK:PCLK = 1:2:4 */
	/* default FCLK is 120 MHz ! */
	ldr	r0, =CLKDIVN
  84:	e59f0460 	ldr	r0, [pc, #1120]	; 4ec <fiq+0x6c>
	mov	r1, #3
  88:	e3a01003 	mov	r1, #3
	str	r1, [r0]
  8c:	e5801000 	str	r1, [r0]
//#endif	/* CONFIG_S3C2400 || CONFIG_S3C2410 */
	mrc	p15, 0, r1, c1, c0, 0	
  90:	ee111f10 	mrc	15, 0, r1, cr1, cr0, {0}
	orr	r1, r1, #0xc0000000	
  94:	e3811103 	orr	r1, r1, #-1073741824	; 0xc0000000
	mcr	p15, 0, r1, c1, c0, 0	/*write ctrl register tekkaman*/
  98:	ee011f10 	mcr	15, 0, r1, cr1, cr0, {0}
	
	
	mov	r1, #CLK_CTL_BASE	/* tekkaman*/
  9c:	e3a01313 	mov	r1, #1275068416	; 0x4c000000
	mov	r2, #MDIV_200	
  a0:	e3a02aa1 	mov	r2, #659456	; 0xa1000
	add	r2, r2, #PSDIV_200	
  a4:	e2822031 	add	r2, r2, #49	; 0x31
	str	r2, [r1, #0x04]
  a8:	e5812004 	str	r2, [r1, #4]
	/*
	 * we do sys-critical inits only at reboot,
	 * not when booting from ram!
	 */
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
	bl	cpu_init_crit
  ac:	eb000056 	bl	20c <cpu_init_crit>
#endif

//#ifndef CONFIG_SKIP_RELOCATE_UBOOT
//relocate:				/* relocate U-Boot to RAM	    */
/***************** CHECK_CODE_POSITION ******************************************/
	adr	r0, _start		/* r0 <- current position of code   */
  b0:	e24f00b8 	sub	r0, pc, #184	; 0xb8
	ldr	r1, _TEXT_BASE		/* test if we run from flash or RAM */
  b4:	e51f107c 	ldr	r1, [pc, #-124]	; 40 <_TEXT_BASE>
	cmp	r0, r1			/* don't reloc during debug         */
  b8:	e1500001 	cmp	r0, r1
	beq	stack_setup
  bc:	0a00003c 	beq	1b4 <stack_setup>
/***************** CHECK_CODE_POSITION ******************************************/

/***************** CHECK_BOOT_FLASH ******************************************/
	ldr	r1, =( (4<<28)|(3<<4)|(3<<2) )		/* address of Internal SRAM  0x4000003C*/
  c0:	e3a011f1 	mov	r1, #1073741884	; 0x4000003c
	mov	r0, #0		/* r0 = 0 */
  c4:	e3a00000 	mov	r0, #0
	str	r0, [r1]
  c8:	e5810000 	str	r0, [r1]


	mov	r1, #0x3c		/* address of men  0x0000003C*/
  cc:	e3a0103c 	mov	r1, #60	; 0x3c
	ldr	r0, [r1]
  d0:	e5910000 	ldr	r0, [r1]
	cmp	r0, #0
  d4:	e3500000 	cmp	r0, #0
	bne	relocate
  d8:	1a000028 	bne	180 <relocate>

	/* recovery  */
	ldr	r0, =(0xdeadbeef)
  dc:	e59f040c 	ldr	r0, [pc, #1036]	; 4f0 <fiq+0x70>
	ldr	r1, =( (4<<28)|(3<<4)|(3<<2) )
  e0:	e3a011f1 	mov	r1, #1073741884	; 0x4000003c
	str	r0, [r1]
  e4:	e5810000 	str	r0, [r1]
#define oNFCONF 0x00
#define oNFCMD 0x04
#define oNFSTAT 0x10

	@ reset NAND
	mov	r1, #NAND_CTL_BASE
  e8:	e3a0144e 	mov	r1, #1308622848	; 0x4e000000
	ldr	r2, =0xf830	@ initial value
  ec:	e59f2400 	ldr	r2, [pc, #1024]	; 4f4 <fiq+0x74>
	str	r2, [r1, #oNFCONF]
  f0:	e5812000 	str	r2, [r1]
	ldr	r2, [r1, #oNFCONF]
  f4:	e5912000 	ldr	r2, [r1]
	bic	r2, r2, #0x800	@ enable chip
  f8:	e3c22b02 	bic	r2, r2, #2048	; 0x800
	str	r2, [r1, #oNFCONF]
  fc:	e5812000 	str	r2, [r1]
	mov	r2, #0xff		@ RESET command
 100:	e3a020ff 	mov	r2, #255	; 0xff
	strb	r2, [r1, #oNFCMD]
 104:	e5c12004 	strb	r2, [r1, #4]
	
	
	mov	r3, #0	@ wait
 108:	e3a03000 	mov	r3, #0

0000010c <nand1>:
nand1:
	add	r3, r3, #0x1
 10c:	e2833001 	add	r3, r3, #1
	cmp	r3, #0xa
 110:	e353000a 	cmp	r3, #10
	blt	nand1
 114:	bafffffc 	blt	10c <nand1>

00000118 <nand2>:

nand2:
	ldr	r2, [r1, #oNFSTAT]	@ wait ready
 118:	e5912010 	ldr	r2, [r1, #16]
	tst	r2, #0x1
 11c:	e3120001 	tst	r2, #1
	beq	nand2
 120:	0afffffc 	beq	118 <nand2>
	
	ldr	r2, [r1, #oNFCONF]
 124:	e5912000 	ldr	r2, [r1]
	orr	r2, r2, #0x800	@ disable chip
 128:	e3822b02 	orr	r2, r2, #2048	; 0x800
	str	r2, [r1, #oNFCONF]
 12c:	e5812000 	str	r2, [r1]
	
	@ get read to call C functions (for nand_read())
	ldr	sp, DW_STACK_START	@ setup stack pointer
 130:	e59fd0d0 	ldr	sp, [pc, #208]	; 208 <DW_STACK_START>
	mov	fp, #0	@ no previous frame, so fp=0
 134:	e3a0b000 	mov	fp, #0
	
	@ copy U-Boot to RAM
	ldr	r0, =TEXT_BASE
 138:	e59f03b8 	ldr	r0, [pc, #952]	; 4f8 <fiq+0x78>
	mov	r1, #0x0
 13c:	e3a01000 	mov	r1, #0
	mov	r2, #LENGTH_UBOOT
 140:	e3a02806 	mov	r2, #393216	; 0x60000
	bl	nand_read_ll
 144:	ebfffffe 	bl	0 <nand_read_ll>
	tst	r0, #0x0
 148:	e3100000 	tst	r0, #0
	beq	ok_nand_read
 14c:	0a000000 	beq	154 <ok_nand_read>

00000150 <bad_nand_read>:

bad_nand_read:
loop2:
	b	loop2	@ infinite loop
 150:	eafffffe 	b	150 <bad_nand_read>

00000154 <ok_nand_read>:


ok_nand_read:
	@ verify
	mov	r0, #0
 154:	e3a00000 	mov	r0, #0
	ldr	r1, =TEXT_BASE
 158:	e59f1398 	ldr	r1, [pc, #920]	; 4f8 <fiq+0x78>
	mov	r2, #0x400	@ 4 bytes * 1024 = 4K-bytes
 15c:	e3a02b01 	mov	r2, #1024	; 0x400

00000160 <go_next>:
go_next:
	ldr	r3, [r0], #4
 160:	e4903004 	ldr	r3, [r0], #4
	ldr	r4, [r1], #4
 164:	e4914004 	ldr	r4, [r1], #4
	teq	r3, r4
 168:	e1330004 	teq	r3, r4
	bne	notmatch
 16c:	1a000002 	bne	17c <loop3>
	subs	r2, r2, #4
 170:	e2522004 	subs	r2, r2, #4
	beq	stack_setup
 174:	0a00000e 	beq	1b4 <stack_setup>
	bne	go_next
 178:	1afffff8 	bne	160 <go_next>

0000017c <loop3>:

notmatch:
loop3:
	b	loop3	@ infinite loop
 17c:	eafffffe 	b	17c <loop3>

00000180 <relocate>:
/***************** NAND_BOOT *************************************************/

/***************** NOR_BOOT *************************************************/
relocate:				/* relocate U-Boot to RAM	    */
      /*********** CHECK_FOR_MAGIC_NUMBER***************/
	ldr	r1, =(0xdeadbeef)
 180:	e59f1368 	ldr	r1, [pc, #872]	; 4f0 <fiq+0x70>
	cmp	r0, r1
 184:	e1500001 	cmp	r0, r1
	bne	loop3
 188:	1afffffb 	bne	17c <loop3>
      /*********** CHECK_FOR_MAGIC_NUMBER***************/
	adr	r0, _start		/* r0 <- current position of code   */
 18c:	e24f0f65 	sub	r0, pc, #404	; 0x194
	ldr	r1, _TEXT_BASE		/* test if we run from flash or RAM */
 190:	e51f1158 	ldr	r1, [pc, #-344]	; 40 <_TEXT_BASE>
	ldr	r2, _armboot_start
 194:	e51f2158 	ldr	r2, [pc, #-344]	; 44 <_armboot_start>
	ldr	r3, _bss_start
 198:	e51f3158 	ldr	r3, [pc, #-344]	; 48 <_bss_start>
	sub	r2, r3, r2		/* r2 <- size of armboot            */
 19c:	e0432002 	sub	r2, r3, r2
	add	r2, r0, r2		/* r2 <- source end address         */
 1a0:	e0802002 	add	r2, r0, r2

000001a4 <copy_loop>:

copy_loop:
	ldmia	r0!, {r3-r10}		/* copy from source address [r0]    */
 1a4:	e8b007f8 	ldm	r0!, {r3, r4, r5, r6, r7, r8, r9, sl}
	stmia	r1!, {r3-r10}		/* copy to   target address [r1]    */
 1a8:	e8a107f8 	stmia	r1!, {r3, r4, r5, r6, r7, r8, r9, sl}
	cmp	r0, r2			/* until source end addreee [r2]    */
 1ac:	e1500002 	cmp	r0, r2
	ble	copy_loop
 1b0:	dafffffb 	ble	1a4 <copy_loop>

000001b4 <stack_setup>:
/***************** NOR_BOOT *************************************************/

	/* Set up the stack						    */
stack_setup:
	ldr	r0, _TEXT_BASE		/* upper 128 KiB: relocated uboot   */
 1b4:	e51f017c 	ldr	r0, [pc, #-380]	; 40 <_TEXT_BASE>
	sub	r0, r0, #CONFIG_SYS_MALLOC_LEN	/* malloc area              */
 1b8:	e2400803 	sub	r0, r0, #196608	; 0x30000
	sub	r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo                 */
 1bc:	e2400080 	sub	r0, r0, #128	; 0x80
#ifdef CONFIG_USE_IRQ
	sub	r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
#endif
	sub	sp, r0, #12		/* leave 3 words for abort-stack    */
 1c0:	e240d00c 	sub	sp, r0, #12

000001c4 <clear_bss>:

clear_bss:
	ldr	r0, _bss_start		/* find start of bss segment        */
 1c4:	e51f0184 	ldr	r0, [pc, #-388]	; 48 <_bss_start>
	ldr	r1, _bss_end		/* stop here                        */
 1c8:	e51f1184 	ldr	r1, [pc, #-388]	; 4c <_bss_end>
	mov	r2, #0x00000000		/* clear                            */
 1cc:	e3a02000 	mov	r2, #0

000001d0 <clbss_l>:

clbss_l:str	r2, [r0]		/* clear loop...                    */
 1d0:	e5802000 	str	r2, [r0]
	add	r0, r0, #4
 1d4:	e2800004 	add	r0, r0, #4
	cmp	r0, r1
 1d8:	e1500001 	cmp	r0, r1
	ble	clbss_l
 1dc:	dafffffb 	ble	1d0 <clbss_l>

	ldr	pc, _start_armboot
 1e0:	e59ff01c 	ldr	pc, [pc, #28]	; 204 <_start_armboot>
#define oGPIO_CON 0x0
/* R/W, Configures the pins of the port */
#define oGPIO_DAT 0x4
#define oGPIO_UP 0x8
/* R/W, Pull-up disable register */
	mov	r1, #GPIO_CTL_BASE
 1e4:	e3a01456 	mov	r1, #1442840576	; 0x56000000
	add	r1, r1, #oGPIO_B
 1e8:	e2811010 	add	r1, r1, #16
	ldr	r2, =0x295551
 1ec:	e59f2308 	ldr	r2, [pc, #776]	; 4fc <fiq+0x7c>
	str	r2, [r1, #oGPIO_CON]
 1f0:	e5812000 	str	r2, [r1]
	mov	r2, #0xff
 1f4:	e3a020ff 	mov	r2, #255	; 0xff
	str	r2, [r1, #oGPIO_UP]
 1f8:	e5812008 	str	r2, [r1, #8]
	ldr	r2, =0x1c1
 1fc:	e59f22fc 	ldr	r2, [pc, #764]	; 500 <fiq+0x80>
	str	r2, [r1, #oGPIO_DAT]
 200:	e5812004 	str	r2, [r1, #4]

00000204 <_start_armboot>:
 204:	00000000 	.word	0x00000000

00000208 <DW_STACK_START>:
 208:	33f0fffc 	.word	0x33f0fffc

0000020c <cpu_init_crit>:
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
cpu_init_crit:
	/*
	 * flush v4 I/D caches
	 */
	mov	r0, #0
 20c:	e3a00000 	mov	r0, #0
	mcr	p15, 0, r0, c7, c7, 0	/* flush v3/v4 cache */
 210:	ee070f17 	mcr	15, 0, r0, cr7, cr7, {0}
	mcr	p15, 0, r0, c8, c7, 0	/* flush v4 TLB */
 214:	ee080f17 	mcr	15, 0, r0, cr8, cr7, {0}

	/*
	 * disable MMU stuff and caches
	 */
	mrc	p15, 0, r0, c1, c0, 0
 218:	ee110f10 	mrc	15, 0, r0, cr1, cr0, {0}
	bic	r0, r0, #0x00002300	@ clear bits 13, 9:8 (--V- --RS)
 21c:	e3c00c23 	bic	r0, r0, #8960	; 0x2300
	bic	r0, r0, #0x00000087	@ clear bits 7, 2:0 (B--- -CAM)
 220:	e3c00087 	bic	r0, r0, #135	; 0x87
	orr	r0, r0, #0x00000002	@ set bit 2 (A) Align
 224:	e3800002 	orr	r0, r0, #2
	orr	r0, r0, #0x00001000	@ set bit 12 (I) I-Cache
 228:	e3800a01 	orr	r0, r0, #4096	; 0x1000
	mcr	p15, 0, r0, c1, c0, 0
 22c:	ee010f10 	mcr	15, 0, r0, cr1, cr0, {0}
	/*
	 * before relocating, we have to setup RAM timing
	 * because memory timing is board-dependend, you will
	 * find a lowlevel_init.S in your board directory.
	 */
	mov	ip, lr
 230:	e1a0c00e 	mov	ip, lr

	bl	lowlevel_init
 234:	ebfffffe 	bl	0 <lowlevel_init>

	mov	lr, ip
 238:	e1a0e00c 	mov	lr, ip
	mov	pc, lr
 23c:	e1a0f00e 	mov	pc, lr

00000240 <undefined_instruction>:
/*
 * exception handlers
 */
	.align  5
undefined_instruction:
	get_bad_stack
 240:	e51fd204 	ldr	sp, [pc, #-516]	; 44 <_armboot_start>
 244:	e24dd802 	sub	sp, sp, #131072	; 0x20000
 248:	e24dd803 	sub	sp, sp, #196608	; 0x30000
 24c:	e24dd088 	sub	sp, sp, #136	; 0x88
 250:	e58de000 	str	lr, [sp]
 254:	e14fe000 	mrs	lr, SPSR
 258:	e58de004 	str	lr, [sp, #4]
 25c:	e3a0d013 	mov	sp, #19
 260:	e169f00d 	msr	SPSR_fc, sp
 264:	e1a0e00f 	mov	lr, pc
 268:	e1b0f00e 	movs	pc, lr
	bad_save_user_regs
 26c:	e24dd048 	sub	sp, sp, #72	; 0x48
 270:	e88d1fff 	stm	sp, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp, ip}
 274:	e51f2238 	ldr	r2, [pc, #-568]	; 44 <_armboot_start>
 278:	e2422802 	sub	r2, r2, #131072	; 0x20000
 27c:	e2422803 	sub	r2, r2, #196608	; 0x30000
 280:	e2422088 	sub	r2, r2, #136	; 0x88
 284:	e892000c 	ldm	r2, {r2, r3}
 288:	e28d0048 	add	r0, sp, #72	; 0x48
 28c:	e28d5034 	add	r5, sp, #52	; 0x34
 290:	e1a0100e 	mov	r1, lr
 294:	e885000f 	stm	r5, {r0, r1, r2, r3}
 298:	e1a0000d 	mov	r0, sp
	bl	do_undefined_instruction
 29c:	ebfffffe 	bl	0 <do_undefined_instruction>

000002a0 <software_interrupt>:

	.align	5
software_interrupt:
	get_bad_stack
 2a0:	e51fd264 	ldr	sp, [pc, #-612]	; 44 <_armboot_start>
 2a4:	e24dd802 	sub	sp, sp, #131072	; 0x20000
 2a8:	e24dd803 	sub	sp, sp, #196608	; 0x30000
 2ac:	e24dd088 	sub	sp, sp, #136	; 0x88
 2b0:	e58de000 	str	lr, [sp]
 2b4:	e14fe000 	mrs	lr, SPSR
 2b8:	e58de004 	str	lr, [sp, #4]
 2bc:	e3a0d013 	mov	sp, #19
 2c0:	e169f00d 	msr	SPSR_fc, sp
 2c4:	e1a0e00f 	mov	lr, pc
 2c8:	e1b0f00e 	movs	pc, lr
	bad_save_user_regs
 2cc:	e24dd048 	sub	sp, sp, #72	; 0x48
 2d0:	e88d1fff 	stm	sp, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp, ip}
 2d4:	e51f2298 	ldr	r2, [pc, #-664]	; 44 <_armboot_start>
 2d8:	e2422802 	sub	r2, r2, #131072	; 0x20000
 2dc:	e2422803 	sub	r2, r2, #196608	; 0x30000
 2e0:	e2422088 	sub	r2, r2, #136	; 0x88
 2e4:	e892000c 	ldm	r2, {r2, r3}
 2e8:	e28d0048 	add	r0, sp, #72	; 0x48
 2ec:	e28d5034 	add	r5, sp, #52	; 0x34
 2f0:	e1a0100e 	mov	r1, lr
 2f4:	e885000f 	stm	r5, {r0, r1, r2, r3}
 2f8:	e1a0000d 	mov	r0, sp
	bl	do_software_interrupt
 2fc:	ebfffffe 	bl	0 <do_software_interrupt>

00000300 <prefetch_abort>:

	.align	5
prefetch_abort:
	get_bad_stack
 300:	e51fd2c4 	ldr	sp, [pc, #-708]	; 44 <_armboot_start>
 304:	e24dd802 	sub	sp, sp, #131072	; 0x20000
 308:	e24dd803 	sub	sp, sp, #196608	; 0x30000
 30c:	e24dd088 	sub	sp, sp, #136	; 0x88
 310:	e58de000 	str	lr, [sp]
 314:	e14fe000 	mrs	lr, SPSR
 318:	e58de004 	str	lr, [sp, #4]
 31c:	e3a0d013 	mov	sp, #19
 320:	e169f00d 	msr	SPSR_fc, sp
 324:	e1a0e00f 	mov	lr, pc
 328:	e1b0f00e 	movs	pc, lr
	bad_save_user_regs
 32c:	e24dd048 	sub	sp, sp, #72	; 0x48
 330:	e88d1fff 	stm	sp, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp, ip}
 334:	e51f22f8 	ldr	r2, [pc, #-760]	; 44 <_armboot_start>
 338:	e2422802 	sub	r2, r2, #131072	; 0x20000
 33c:	e2422803 	sub	r2, r2, #196608	; 0x30000
 340:	e2422088 	sub	r2, r2, #136	; 0x88
 344:	e892000c 	ldm	r2, {r2, r3}
 348:	e28d0048 	add	r0, sp, #72	; 0x48
 34c:	e28d5034 	add	r5, sp, #52	; 0x34
 350:	e1a0100e 	mov	r1, lr
 354:	e885000f 	stm	r5, {r0, r1, r2, r3}
 358:	e1a0000d 	mov	r0, sp
	bl	do_prefetch_abort
 35c:	ebfffffe 	bl	0 <do_prefetch_abort>

00000360 <data_abort>:

	.align	5
data_abort:
	get_bad_stack
 360:	e51fd324 	ldr	sp, [pc, #-804]	; 44 <_armboot_start>
 364:	e24dd802 	sub	sp, sp, #131072	; 0x20000
 368:	e24dd803 	sub	sp, sp, #196608	; 0x30000
 36c:	e24dd088 	sub	sp, sp, #136	; 0x88
 370:	e58de000 	str	lr, [sp]
 374:	e14fe000 	mrs	lr, SPSR
 378:	e58de004 	str	lr, [sp, #4]
 37c:	e3a0d013 	mov	sp, #19
 380:	e169f00d 	msr	SPSR_fc, sp
 384:	e1a0e00f 	mov	lr, pc
 388:	e1b0f00e 	movs	pc, lr
	bad_save_user_regs
 38c:	e24dd048 	sub	sp, sp, #72	; 0x48
 390:	e88d1fff 	stm	sp, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp, ip}
 394:	e51f2358 	ldr	r2, [pc, #-856]	; 44 <_armboot_start>
 398:	e2422802 	sub	r2, r2, #131072	; 0x20000
 39c:	e2422803 	sub	r2, r2, #196608	; 0x30000
 3a0:	e2422088 	sub	r2, r2, #136	; 0x88
 3a4:	e892000c 	ldm	r2, {r2, r3}
 3a8:	e28d0048 	add	r0, sp, #72	; 0x48
 3ac:	e28d5034 	add	r5, sp, #52	; 0x34
 3b0:	e1a0100e 	mov	r1, lr
 3b4:	e885000f 	stm	r5, {r0, r1, r2, r3}
 3b8:	e1a0000d 	mov	r0, sp
	bl	do_data_abort
 3bc:	ebfffffe 	bl	0 <do_data_abort>

000003c0 <not_used>:

	.align	5
not_used:
	get_bad_stack
 3c0:	e51fd384 	ldr	sp, [pc, #-900]	; 44 <_armboot_start>
 3c4:	e24dd802 	sub	sp, sp, #131072	; 0x20000
 3c8:	e24dd803 	sub	sp, sp, #196608	; 0x30000
 3cc:	e24dd088 	sub	sp, sp, #136	; 0x88
 3d0:	e58de000 	str	lr, [sp]
 3d4:	e14fe000 	mrs	lr, SPSR
 3d8:	e58de004 	str	lr, [sp, #4]
 3dc:	e3a0d013 	mov	sp, #19
 3e0:	e169f00d 	msr	SPSR_fc, sp
 3e4:	e1a0e00f 	mov	lr, pc
 3e8:	e1b0f00e 	movs	pc, lr
	bad_save_user_regs
 3ec:	e24dd048 	sub	sp, sp, #72	; 0x48
 3f0:	e88d1fff 	stm	sp, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp, ip}
 3f4:	e51f23b8 	ldr	r2, [pc, #-952]	; 44 <_armboot_start>
 3f8:	e2422802 	sub	r2, r2, #131072	; 0x20000
 3fc:	e2422803 	sub	r2, r2, #196608	; 0x30000
 400:	e2422088 	sub	r2, r2, #136	; 0x88
 404:	e892000c 	ldm	r2, {r2, r3}
 408:	e28d0048 	add	r0, sp, #72	; 0x48
 40c:	e28d5034 	add	r5, sp, #52	; 0x34
 410:	e1a0100e 	mov	r1, lr
 414:	e885000f 	stm	r5, {r0, r1, r2, r3}
 418:	e1a0000d 	mov	r0, sp
	bl	do_not_used
 41c:	ebfffffe 	bl	0 <do_not_used>

00000420 <irq>:

#else

	.align	5
irq:
	get_bad_stack
 420:	e51fd3e4 	ldr	sp, [pc, #-996]	; 44 <_armboot_start>
 424:	e24dd802 	sub	sp, sp, #131072	; 0x20000
 428:	e24dd803 	sub	sp, sp, #196608	; 0x30000
 42c:	e24dd088 	sub	sp, sp, #136	; 0x88
 430:	e58de000 	str	lr, [sp]
 434:	e14fe000 	mrs	lr, SPSR
 438:	e58de004 	str	lr, [sp, #4]
 43c:	e3a0d013 	mov	sp, #19
 440:	e169f00d 	msr	SPSR_fc, sp
 444:	e1a0e00f 	mov	lr, pc
 448:	e1b0f00e 	movs	pc, lr
	bad_save_user_regs
 44c:	e24dd048 	sub	sp, sp, #72	; 0x48
 450:	e88d1fff 	stm	sp, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp, ip}
 454:	e51f2418 	ldr	r2, [pc, #-1048]	; 44 <_armboot_start>
 458:	e2422802 	sub	r2, r2, #131072	; 0x20000
 45c:	e2422803 	sub	r2, r2, #196608	; 0x30000
 460:	e2422088 	sub	r2, r2, #136	; 0x88
 464:	e892000c 	ldm	r2, {r2, r3}
 468:	e28d0048 	add	r0, sp, #72	; 0x48
 46c:	e28d5034 	add	r5, sp, #52	; 0x34
 470:	e1a0100e 	mov	r1, lr
 474:	e885000f 	stm	r5, {r0, r1, r2, r3}
 478:	e1a0000d 	mov	r0, sp
	bl	do_irq
 47c:	ebfffffe 	bl	0 <do_irq>

00000480 <fiq>:

	.align	5
fiq:
	get_bad_stack
 480:	e51fd444 	ldr	sp, [pc, #-1092]	; 44 <_armboot_start>
 484:	e24dd802 	sub	sp, sp, #131072	; 0x20000
 488:	e24dd803 	sub	sp, sp, #196608	; 0x30000
 48c:	e24dd088 	sub	sp, sp, #136	; 0x88
 490:	e58de000 	str	lr, [sp]
 494:	e14fe000 	mrs	lr, SPSR
 498:	e58de004 	str	lr, [sp, #4]
 49c:	e3a0d013 	mov	sp, #19
 4a0:	e169f00d 	msr	SPSR_fc, sp
 4a4:	e1a0e00f 	mov	lr, pc
 4a8:	e1b0f00e 	movs	pc, lr
	bad_save_user_regs
 4ac:	e24dd048 	sub	sp, sp, #72	; 0x48
 4b0:	e88d1fff 	stm	sp, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp, ip}
 4b4:	e51f2478 	ldr	r2, [pc, #-1144]	; 44 <_armboot_start>
 4b8:	e2422802 	sub	r2, r2, #131072	; 0x20000
 4bc:	e2422803 	sub	r2, r2, #196608	; 0x30000
 4c0:	e2422088 	sub	r2, r2, #136	; 0x88
 4c4:	e892000c 	ldm	r2, {r2, r3}
 4c8:	e28d0048 	add	r0, sp, #72	; 0x48
 4cc:	e28d5034 	add	r5, sp, #52	; 0x34
 4d0:	e1a0100e 	mov	r1, lr
 4d4:	e885000f 	stm	r5, {r0, r1, r2, r3}
 4d8:	e1a0000d 	mov	r0, sp
	bl	do_fiq
 4dc:	ebfffffe 	bl	0 <do_fiq>
 4e0:	4a000008 	.word	0x4a000008
 4e4:	000007ff 	.word	0x000007ff
 4e8:	4a00001c 	.word	0x4a00001c
 4ec:	4c000014 	.word	0x4c000014
 4f0:	deadbeef 	.word	0xdeadbeef
 4f4:	0000f830 	.word	0x0000f830
 4f8:	33f80000 	.word	0x33f80000
 4fc:	00295551 	.word	0x00295551
 500:	000001c1 	.word	0x000001c1
 504:	e1a00000 	nop			; (mov r0, r0)
 508:	e1a00000 	nop			; (mov r0, r0)
 50c:	e1a00000 	nop			; (mov r0, r0)
 510:	e1a00000 	nop			; (mov r0, r0)
 514:	e1a00000 	nop			; (mov r0, r0)
 518:	e1a00000 	nop			; (mov r0, r0)
 51c:	e1a00000 	nop			; (mov r0, r0)