Zedboard---实验五点亮另一个数码管

Zedboard—实验五点亮另一个数码管

本节实验将点亮上节实验中的另一个数码管。通过频率为500kHz的ssdcat信号来选通两位数码管。开关输入将用到低位switch[3:0]和高位switch[7:4]。

计数1ms

输入时钟信号频率为100MHz，计数器计数100000个周期，产生一个脉冲。这里使用一个寄存器来实现：

integer count = 0;
reg ms_pulse = 0;
always @(posedge clk)
  if (count == 99999)
    begin
      count <= 0;
      ms_pulse <= 1;
    end
  else
    begin
      count <= count+1;
      ms_pulse <= 0;
    end

上述代码实现每隔1个毫秒产生一个脉冲，由此产生ssdcat信号：

always @(posedge clk)
  if (ms_pulse) ssdcat <= ~ssdcat;

不要忘了初始化ssdcat为零：

initial ssdcat = 0;

如上设计，可以看到两个数码管同时显示，但是没有之前那么亮。当然，显示数字是相同的，因为驱动ssd输出值都是通过Switch[3:0]。

是两个数码管显示不同

交替显示两个数码管，同样输入也使用case语句。声明digit的4位输入：

wire [3:0] digit;

接下来设置数字显示值，并且适应位选信号：

assign digit = ssdcat? switch[3:0] : switch[7:4];

代码文件

top.v

`timescale 1ns / 1ns
module top
  (
   input clk,
   input [7:0] switch,
   output reg [7:0] led,
   output reg [6:0] ssd,
   output reg ssdcat
   );

  always @(posedge clk) led <= switch;

  wire [3:0]  digit;
  always @(posedge clk)
    case (digit)
      0: ssd <= 7'b1111110;
      1: ssd <= 7'b0110000;
      2: ssd <= 7'b1101101;
      3: ssd <= 7'b1111001;
      4: ssd <= 7'b0110011;
      5: ssd <= 7'b1011011;
      6: ssd <= 7'b1011111;
      7: ssd <= 7'b1110000;
      8: ssd <= 7'b1111111;
      9: ssd <= 7'b1110011;
      10: ssd <= 7'b1110111;
      11: ssd <= 7'b0011111;
      12: ssd <= 7'b1001110;
      13: ssd <= 7'b0111101;
      14: ssd <= 7'b1001111;
      15: ssd <= 7'b1000111;
    endcase

  integer     count = 0;
  reg         ms_pulse = 0;
  always @(posedge clk)
    if (count == 99999)
      begin
    count <= 0;
    ms_pulse <= 1;
      end
    else
      begin
    count <= count+1;
    ms_pulse <= 0;
      end

  always @(posedge clk)
    if (ms_pulse) ssdcat <= ~ssdcat;

  assign digit = ssdcat ? switch[3:0] : switch[7:4];

endmodule

硬件效果

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原文连接