RTL9000BRG调试总结

于 2024-05-13 18:53:20 发布
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}, {
	.phy_id		= 0x001cc916,
	.name		= "RTL8211F Gigabit Ethernet",
	.phy_id_mask	= 0x001fffff,
	.features	= PHY_GBIT_FEATURES,
	.flags		= PHY_HAS_INTERRUPT,
	.config_aneg	= &genphy_config_aneg,
	.config_init	= &rtl8211f_config_init,
	.read_status	= &genphy_read_status,
	.ack_interrupt	= &rtl8211f_ack_interrupt,
	.config_intr	= &rtl8211f_config_intr,
	.suspend	= genphy_suspend,
	.resume		= genphy_resume,
},

};


所以需要自己适配RTL9000。


## 1.配置设备树

&ethernet {
status = “okay”;
phy-handle = <&phy1>;
phy-mode = “rgmii-id”;
phy-reset-gpios = <112>;
phy-reset-duration = <12>;
phy-reset-post-delay = <10>;
mdio {
#address-cells = <0x1>;
#size-cells = <0x0>;
phy1: phy@1 {
compatible = “RTL8211F Gigabit Ethernet”,“ethernet-phy-ieee802.3-c45”;
reg = <0x1>;
};
};
};


## 2.明确phy id


![](https://img-blog.csdnimg.cn/8940842c14474a2f9c59151cb3179666.png)


 根据寄存器值可以确定phy id是0x001ccb00


## 3.填充驱动

/*

  • drivers/net/phy/realtek.c
  • Driver for Realtek PHYs
  • Author: Johnson Leung r58129@freescale.com
  • Copyright © 2004 Freescale Semiconductor, Inc.
  • This program is free software; you can redistribute it and/or modify it
  • under the terms of the GNU General Public License as published by the
  • Free Software Foundation; either version 2 of the License, or (at your
  • option) any later version.

*/
#include <linux/phy.h>
#include <linux/module.h>
#include <linux/delay.h>

#define RTL821x_PHYSR 0x11
#define RTL821x_PHYSR_DUPLEX 0x2000
#define RTL821x_PHYSR_SPEED 0xc000
#define RTL821x_INER 0x12
#define RTL821x_INER_INIT 0x6400
#define RTL821x_INSR 0x13
#define RTL8211E_INER_LINK_STATUS 0x400

#define RTL8211F_INER_LINK_STATUS 0x0010
#define RTL8211F_INSR 0x1d
#define RTL8211F_PAGE_SELECT 0x1f
#define RTL8211F_TX_DELAY 0x100

#define MIIM_RTL9000_SRAM_ADDR 0x1b
#define MIIM_RTL9000_SRAM_DATA 0x1c
#define MIIM_RTL9000_PAGE_SELECT 0x1f

/*

  • For RTL9000 RGMII Control Registers
  • special register
    */
    #define MIIM_RTL9000_RGRXCR 0xd082
    #define MIIM_RTL9000_TX_DELAY 0x10<<8
    #define MIIM_RTL9000_PHY_STATUS 0x1a
    #define MIIM_RTL9000_PHYSTAT_LINK 0x0004
    #define MIIM_RTL9000_PHYSTAT_DUPLEX 0x0100
    #define MIIM_RTL9000_PHYSTAT_SPEED 0x2040

unsigned int param_check[6*3]={0, 0x8017, 0xFB03, 0, 0x8092, 0x6000,
0, 0x80AF, 0x6000, 0, 0x807D, 0x4443, 0, 0x809A, 0x4443, 0, 0x81A3, 0x0F00};

MODULE_DESCRIPTION(“Realtek PHY driver”);
MODULE_AUTHOR(“Johnson Leung”);
MODULE_LICENSE(“GPL”);

static int rtl821x_ack_interrupt(struct phy_device *phydev)
{
int err;

err = phy_read(phydev, RTL821x_INSR);

return (err < 0) ? err : 0;

}

static int rtl8211f_ack_interrupt(struct phy_device *phydev)
{
int err;

phy_write(phydev, RTL8211F_PAGE_SELECT, 0xa43);
err = phy_read(phydev, RTL8211F_INSR);
/* restore to default page 0 */
phy_write(phydev, RTL8211F_PAGE_SELECT, 0x0);

return (err < 0) ? err : 0;

}

static int rtl8211b_config_intr(struct phy_device *phydev)
{
int err;

if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
	err = phy_write(phydev, RTL821x_INER,
			RTL821x_INER_INIT);
else
	err = phy_write(phydev, RTL821x_INER, 0);

return err;

}

static int rtl8211e_config_intr(struct phy_device *phydev)
{
int err;

if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
	err = phy_write(phydev, RTL821x_INER,
			RTL8211E_INER_LINK_STATUS);
else
	err = phy_write(phydev, RTL821x_INER, 0);

return err;

}

static int rtl8211f_config_intr(struct phy_device *phydev)
{
int err;

if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
	err = phy_write(phydev, RTL821x_INER,
			RTL8211F_INER_LINK_STATUS);
else
	err = phy_write(phydev, RTL821x_INER, 0);

return err;

}

static int rtl8211f_config_init(struct phy_device *phydev)
{
int ret;
u16 reg;

ret = genphy_config_init(phydev);
if (ret < 0)
	return ret;

phy_write(phydev, RTL8211F_PAGE_SELECT, 0xd08);
reg = phy_read(phydev, 0x11);

/* enable TX-delay for rgmii-id and rgmii-txid, otherwise disable it */
if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
    phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
	reg |= RTL8211F_TX_DELAY;
else
	reg &= ~RTL8211F_TX_DELAY;

phy_write(phydev, 0x11, reg);
/* restore to default page 0 */
phy_write(phydev, RTL8211F_PAGE_SELECT, 0x0);

return 0;

}

static void RTL9000Bxx_Initial_Config_Erratum1(struct phy_device *phydev)
{
int io_data = 0;
int timer = 2000;
//sample_code 04
//phy_write(phydev, 0x1F, 0x0A43);
phy_write(phydev, 0x1B, 0x8017);
phy_write(phydev, 0x1C, 0xFB03); // PHY patch request
phy_write(phydev, 0x1B, 0x8092);
phy_write(phydev, 0x1C, 0x6000);
phy_write(phydev, 0x1B, 0x80AF);
phy_write(phydev, 0x1C, 0x6000);
phy_write(phydev, 0x1B, 0x807D);
phy_write(phydev, 0x1C, 0x4443);
phy_write(phydev, 0x1B, 0x809A);
phy_write(phydev, 0x1C, 0x4443);
phy_write(phydev, 0x1B, 0x81A3);
phy_write(phydev, 0x1C, 0x0F00);
phy_write(phydev, 0x1F, 0x0A81);
phy_write(phydev, 0x12, 0x0004);
phy_write(phydev, 0x1B, 0x83C8);
phy_write(phydev, 0x1C, 0x0005);
phy_write(phydev, 0x1F, 0x0A5C);
phy_write(phydev, 0x12, 0x0003);
phy_write(phydev, 0x1B, 0xB820);
phy_write(phydev, 0x1C, 0x0010);
phy_write(phydev, 0x1B, 0xB830);
phy_write(phydev, 0x1C, 0x8000);
//phy_write(phydev, 0x1B, 0xB800);
do {
phy_write(phydev, 0x1B, 0xB800);
io_data = (phy_read(phydev, 0x1C)) & 0x40;
timer–;
if (timer == 0) {
timer = 2000;
break;
}
} while (io_data == 0);

phy_write(phydev, 0x1B, 0x8020);
phy_write(phydev, 0x1C, 0x3300);
phy_write(phydev, 0x1B, 0xB82E);
phy_write(phydev, 0x1C, 0x0001);
phy_write(phydev, 0x1B, 0xB820);
phy_write(phydev, 0x1C, 0x0290);
phy_write(phydev, 0x1B, 0xA012);
phy_write(phydev, 0x1C, 0x0000);
phy_write(phydev, 0x1B, 0xA014);
phy_write(phydev, 0x1C, 0x401C);
phy_write(phydev, 0x1C, 0xA610);
phy_write(phydev, 0x1C, 0x8520);
phy_write(phydev, 0x1C, 0xA510);
phy_write(phydev, 0x1C, 0x21F4);
phy_write(phydev, 0x1B, 0xA01A);
phy_write(phydev, 0x1C, 0x0000);
phy_write(phydev, 0x1B, 0xA000);
phy_write(phydev, 0x1C, 0x11EF);
phy_write(phydev, 0x1B, 0xB820);
phy_write(phydev, 0x1C, 0x0210);
phy_write(phydev, 0x1B, 0xB82E);
phy_write(phydev, 0x1C, 0x0000);
phy_write(phydev, 0x1B, 0x8020);
phy_write(phydev, 0x1C, 0x0000);
phy_write(phydev, 0x1B, 0xB820);
phy_write(phydev, 0x1C, 0x0000);
//phy_write(phydev, 0x1B, 0xB800);
do {
	phy_write(phydev, 0x1B, 0xB800);
	io_data = (phy_read(phydev, 0x1C)) & 0x40;
	timer--;
	if (timer == 0) {
		break;
	}
} while (io_data != 0);

}

static int RTL9000Bxx_init(struct phy_device *phydev)
{
int mdio_data = 0;
int ret;
int set_master = 0;
int power_section = 5;

unsigned int mdio_data_chk = 0;
unsigned int page;
unsigned int reg, i;

/*  check PHY accessible  */
while (mdio_data != 0x0003) {
	phy_write(phydev, 0x1F, 0x0A42);
	mdio_data = phy_read(phydev, 0x10);
	mdio_data = mdio_data & 0x0007;
}

/*  hardware reset  */
// phy_write(phydev, 0x1B, 0xDD00);
// mdio_data = phy_read(phydev, 0x1C);
// phy_write(phydev, 0x1C, (mdio_data | 0x0020));

phy_write(phydev, 0x1F, 0x0A42);//change page to default value
//check PHY accessible

mdio_data = 0;
while (mdio_data != 0x0003) {
	mdio_data = phy_read(phydev, 0x10);
	mdio_data = mdio_data & 0x0007;
}

/*  init parameter  */
RTL9000Bxx_Initial_Config_Erratum1(phydev);

/*  check init success  */
for(i = 0; i < 6*3; i = i+3) {
	page = param_check[i];
	mdio_data_chk = param_check[i+2];
	reg = param_check[i+1];
	if(page == 0) {
		phy_write(phydev, 0x1B, reg);
		mdio_data = phy_read(phydev, 0x1C);
	} else {
		phy_write(phydev, 0x1F, reg);
		mdio_data = phy_read(phydev, reg);
	}
	if(mdio_data_chk!= mdio_data) {
		printk(("%dth param error page=0x%04X reg=0x%04X data=0x%04X\n",
			i/3, page, reg, mdio_data));
		printk("phyInit error\n");
	}
}
printk("phy Init success\n");

/*  I/O Power Sllection  */
phy_write(phydev, 0x1F, 0x0A4C);//change page to default value
mdio_data = phy_read(phydev, 0x12);
mdio_data &= 0xC7FF;
mdio_data |= 4 << 11;
phy_write(phydev, 0x12, mdio_data);



/***************************here is optional **********************/
/*  role setting  */
if (set_master == 1) {
	// Master or Slave mode depends on customer's application.
	mdio_data = phy_read(phydev, 9);
	phy_write(phydev, 9, (mdio_data | 0x0800));	// Set as Master
} else {
	mdio_data = phy_read(phydev, 9);
	phy_write(phydev, 9, (mdio_data & 0xF7FF));	// Set as Slave
}
//.....other applications
/*****************************************************************/


/*  power supply selection */
switch (power_section) {
case 0://external 3.3V
	phy_write(phydev, 0x1F, 0x0A43); //change page to 0xa43
	phy_write(phydev, 0x1B, 0xDC06);
	phy_write(phydev, 0x1C, 0x0DF8);
	break;
case 1://internal LDO 2.5V
	phy_write(phydev, 0x1F, 0x0A43);
	phy_write(phydev, 0x1B, 0xDC06);
	phy_write(phydev, 0x1C, 0x5DF9);
	break;
case 2://external 2.5V
	phy_write(phydev, 0x1F, 0x0A43);
	phy_write(phydev, 0x1B, 0xDC06);
	phy_write(phydev, 0x1C, 0xDDF9);
	break;
case 3://internal LDO 1.8v
	phy_write(phydev, 0x1F, 0x0A43);
	phy_write(phydev, 0x1B, 0xDC06);
	phy_write(phydev, 0x1C, 0xADFA);
	break;
case 4://external 1.8v
	phy_write(phydev, 0x1F, 0x0A43);
	phy_write(phydev, 0x1B, 0xDC06);
	phy_write(phydev, 0x1C, 0xEDFA);
	break;
case 5://RTL9000BRG
	//phy_write(phydev, 0x1F, 0x0A43);
	phy_write(phydev, 0x1B, 0xD414);
	ret = (phy_read(phydev, 0x1C)) | 0x1010;
	phy_write(phydev, 0x1C, ret);

	phy_write(phydev, 0x1B, 0xD416);
	ret = (phy_read(phydev, 0x1C)) | 0x1010;
	phy_write(phydev, 0x1C, ret);

	phy_write(phydev, 0x1B, 0xD418);
	ret = (phy_read(phydev, 0x1C)) | 0x1000;
	phy_write(phydev, 0x1C, ret);

	phy_write(phydev, 0x1B, 0xD41A);
	ret = (phy_read(phydev, 0x1C)) | 0x1000;
	phy_write(phydev, 0x1C, ret);
	phy_write(phydev, 0x1B, 0xD42E);
	phy_write(phydev, 0x1C, 0x7E7E);
}

/* Settting delay */
phy_write(phydev, 0x1F, 0x0a43);
phy_write(phydev, 0x1B, 0xD082);
reg = phy_read(phydev, 0x1C);

/* enable TX-delay for rgmii-id and rgmii-txid, otherwise disable it */
if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
    phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
	reg &= 0xFCF8;
	reg |= 7;      //RX delay
	//reg |= 1 << 8;   //TX delay
} else {
	reg &= ~(0x10 << 8);
}
phy_write(phydev, 0x1B, 0xD082);
phy_write(phydev, 0x1C, reg);
phy_write(phydev, 0x1F, 0xa42);



//software reset
phy_write(phydev, 0, 0x8000);	// PHY soft-reset
mdelay(30);

/*  Check soft-reset complete  */
mdio_data = 0;
mdio_data = phy_read(phydev, 0);
int num = 0;
while (mdio_data != 0x2100) {
	mdio_data = phy_read(phydev, 0);
	if(num == 9)
		break;
	++num;
}

return 0;

}

static int rtl9000_config_init(struct phy_device *phydev)
{
unsigned int reg;
phy_write(phydev, 0, 0x8000); // PHY soft-reset
mdelay(30);

RTL9000Bxx_init(phydev);

/* Set green LED for Link, yellow LED for Active */
// phy_write(phydev, MDIO_DEVAD_NONE,
// 	  MIIM_RTL9000_PAGE_SELECT, 0xd04);

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RTL9047A 为车用乙太网single chip 交换机方案,如下图port0~port3 总共提供4ports 100BASE-T1,不用外挂PHY可节省cost 及PCB空间; port4为 selection port可选择设定100BASE-T1或SGMII,其SGMII个外接CPU或对接相同型号switch做cascade扩充; port5为 selection port可选择设定传统100base-TX FE PHY, SGMII或 RGMII/MII/RMII,其100base-TX 界面作为车载Diagnostic界面; port6为RGMII/MII/RMII 界面,可用来外接CPU或扩充网路界面等应用。 RTL9047A相较于NXP SJA1105 多四口internal 100base-T1 PHY,可节省车厂bom cost并增加PCB layout设计弹性。 RTL9047AA提供的100Base-T1符合标准是IEEE 802.3bw规范,它具有100 Mb / s的速率,通过双绞线（T1）进行全双工通信。 能够支持线材至少15米,而相较于车用传统LIN、CAN 界面,可以提高更好的频宽,并能和车用交换器及资料中心做连接,达到多个节点装置互相通信,建构各种不同所需的网路拓朴 ,此外,具有低辐射,高RF抗扰度和更长距离通信的能力。 根据 Open Alliance TC1标准规范,车载乙太网路测试项目EMC、IOP、 PCS 、PMA、PHYC, RTL9047AA 已在Open Alliance认证实验室通过以上所有测项,并可提供测试报告给车厂评估. (一)友尚FAE能协助提供(申请)开发者需要的参考文件及软件包,如下; 1.RTL9047AA-VC_DataSheet 2.RTL9047AA-VC_Reference_Schematic 3.RTL904Xxx_Series_Demo_Board_User_Guide(让开发者快速理解switch应用及操作) 4.RTL904Xxx-VC_Schematic_Checklist(方便开发者检视硬体设计) 5.RTL904Xxx_Series_SDK_API_Programming_Guide(软件开发用) 6.Realtek Automotive Switch Tool(turnkey tool,全面UI界面设定产出image,节省软件开发effort) (二)友尚FAE可协助开发者硬件线路及layout review (三)友尚FAE可协助软体 API整合开发,switch tool应用及网管整合协助 (四)请车厂开发单位在大大购平台购买EVB board后,并向大大通或代理商(友尚)申请porting和网关sample code,节省开发时间。 RTL9047AA提供SPI slave\SMI slave\I2C slave界面接到SOC,让开发者将RTL9047AA API code 包入CPU系统后可以动态设定功能,也可节省FLASH元件cost。 开发者也可直接套用API里的sample code造出I2C\SMI或SPI来porting RTL9047AA,ex:src/rtk_i2c.c 、src/rtk_mdc.c 、 src/rtk_spi.c RTL9047AA API code,可让开发者动态可调性的客制化设定网管必备功能,例如以下范例: 1.Port-Base VLAN feature,以下设定将Port0~Port2设为Group VLAN1,将Port3~Port5设为Group VLAN2,形成不同VLAN Group之间无法传递资料,要在同一个VLAN Group才能收送资料。 /* initialize VLAN */ rtk_vlan_init (); /* all the ports are in the default VLAN 1 after VLAN is initialized. Modify it as follows VLAN1 member: port0, port1, port2; VLAN2 member: port3, port4, port5 */ rtk_portmask_t mbrmsk, untagmsk; rtk_vlan_t VLAN1, VLAN2; VLAN1 = 100; VLAN2 = 200; mbrmsk.bits[0]=0x07; /* port 0~ port 2*/ untagmsk.bits[0]=0x3F; rtk_vlan_set(VLAN1, mbrmsk, untagmsk, 0); mbrmsk.bits[0]=0x38; /* port 3~
rtl9000bf pdf
最新发布
01-12
RTL9000BF是一款集成了大容量随机存取存储器（RAM）和写保护功能的低功耗微控制器。它采用了CMOS技术，具有低功耗、高性能的特点，适用于各种电子设备中的数据存储和处理应用。 这款微控制器的英文名称为"Real-Time...

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