jz2440_LCD硬件分析

1. jz2440v3 LCD 插座原理图

从原理图看到，我们的 LCD 插座只接了 16 根数据线（其中红色 R1 ~ R5，绿色 G0 ~ G5，蓝色 B1~ B5）。也就是说我们使用的是 S3C2440A 芯片的 LCD 控制器中的 16bpp 的显示方式。并无法完全发挥 TFT LCD 屏幕的最高色域 32 位真彩色的能力。

2. A043-24-TT-11 液晶屏

2.1 引脚功能

2.2.1 TFT LCD Panel Driving Section

显示部分的引脚功能如下：

2.1.2 Touch Screen Panel Section

触摸屏的功能如下：

3. s3c2440 LCD控制器

3.1 概述

The LCD controller in the S3C2440A consists of the logic for transferring LCD image data from a video buffer located in system memory to an external LCD driver.

The LCD controller supports monochrome（黑白色）, 2-bit per pixel (4-level gray scale) or 4-bit per pixel (16-level gray scale) mode on a monochrome LCD, using a time-based dithering algorithm（基于时间的混色算法） and Frame Rate Control (FRC) method

and it can be interfaced with a color LCD panel at 8-bit per pixel (256-level color) and 12-bit per pixel (4096-level color) for interfacing with STN LCD. It can support 1-bit per pixel, 2-bit per pixel, 4-bit per pixel, and 8-bit per pixel for interfacing with the palletized TFT color LCD panel, and 16-bit per pixel and 24-bit per pixel for non-palletized true-color display.

LCD controller 支持 monochrome 和 color 两种色彩显示方式。

• monochrome（黑白显示）：支持2比特表示的4度灰，4比特表示的16度灰。

• color（彩色显示）：对于 STN LCD 支持8比特的256种色彩，12比特表示的4096种色彩；对于 TFT LCD 支持1比特、2比特、4比特、8比特每像素点的调色板显示和16比特、24比特的真彩色显示。

  palletized color 意思是通过调用调色板得到的实际颜色，实际上就是查找颜色表。一般是为了减少表示颜色的数据量。

  比如：RGB 三色表，每种颜色用 8bits 表示，可表示成 256色/灰度（2的8次方）。

  如果每个显示点数据用3字节表示，就没必要去查找调色板，直接用原始数据表示即可，这就是为什么上面会说：24-bit per pixel non-palletized true-color displays ！

The LCD controller can be programmed to support different requirements on the screen related to the number of horizontal and vertical pixels, data line width for the data interface, interface timing, and refresh rate.

3.2 FEATURES（特性）

由于我们屏幕使用的是 TFT 屏幕，因此我们下面只关注 TFT 部分。

3.2.1 特殊特性

STN LCD Displays:

— Supports 3 types of LCD panels: 4-bit dual scan, 4-bit single scan, and 8-bit single scan display type

— Supports the monochrome, 4 gray levels, and 16 gray levels

— Supports 256 colors and 4096 colors for color STN LCD panel

— Supports multiple screen size

Typical actual screen size: 640 x 480, 320 x 240, 160 x 160, and others

Maximum virtual screen size is 4Mbytes.

Maximum virtual screen size in 256 color mode: 4096 x 1024, 2048 x 2048, 1024 x 4096, and others

TFT LCD Displays:

• Supports 1, 2, 4 or 8-bpp (bit per pixel) palletized color displays for TFT

• Supports 16, 24-bpp non-palletized true-color displays for color TFT

• Supports maximum 16M color TFT at 24bit per pixel mode

• Supports multiple screen size

  • Typical actual screen size: 640 x 480, 320 x 240, 160 x 160, and others

  • Maximum virtual screen size is 4Mbytes.

  • Maximum virtual screen size in 64K color mode: 2048 x 1024 and others

3.2.2 COMMON FEATURES（通用特性）

The LCD controller has a dedicated DMA that supports to fetch the image data from video buffer（专用的DMA） located in system memory. Its features also include:

• Dedicated interrupt functions (INT_FrSyn and INT_FiCnt) （专用的外部中断）

• The system memory is used as the display memory. （使用系统内存作为显存）

• Supports Multiple Virtual Display Screen (Supports Hardware Horizontal/Vertical Scrolling) （多种显示方式）

• Programmable timing control for different display panels （可编程的时间控制 用于不同的液晶面板）

• Supports little and big-endian byte ordering, as well as WinCE data formats

• Supports 2-type SEC TFT LCD panel

  • (SAMSUNG 3.5” Portrait / 256K Color /Reflective and Transflective a-Si TFT LCD)

  • LTS350Q1-PD1: TFT LCD panel with touch panel and front light unit (Reflective type)

  • LTS350Q1-PD2: TFT LCD panel only

  • LTS350Q1-PE1: TFT LCD panel with touch panel and front light unit (Transflective type)

  • LTS350Q1-PE2: TFT LCD panel only

NOTE

WinCE doesn’t support the 12-bit packed data format. Please check if WinCE can support the 12-bit color-mode.

3.3 BLOCK DIAGRAM

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The S3C2440A LCD controller is used to transfer the video data and to generate the necessary control signals, such as VFRAME, VLINE, VCLK, VM, and so on. In addition to the control signals, the S3C2440A has the data ports for video data, which are VD[23:0] as shown in Figure 15-1.

The LCD controller consists of a REGBANK, LCDCDMA, VIDPRCS, TIMEGEN, and LPC3600 (See the Figure 15-1 LCD Controller Block Diagram).

• The REGBANK has 17 programmable register sets and 256x16 palette memory which are used to configure the LCD controller. （REGBANK 中有17个可编程的寄存器集合和256x16的调色内存）
• The LCDCDMA is a dedicated DMA, which can transfer the video data in frame memory to LCD driver automatically. By using this special DMA, the video data can be displayed on the screen without CPU intervention. （LCDCDMA 是专用于LCD使用的DMA）
• The VIDPRCS receives the video data from the LCDCDMA and sends the video data through the VD[23:0] data ports to the LCD driver after changing them into a suitable data format, for example 4/8-bit single scan or 4-bit dual scan display mode. （VIDPRCS 通过数据总线 VD[23:0] 将 LCDCDMA 的数据发送给 LCD 液晶屏）
• The TIMEGEN consists of programmable logic to support the variable requirements of interface timing and rates commonly found in different LCD drivers. The TIMEGEN block generates VFRAME, VLINE, VCLK, VM, and so on. （TIMEGEN 用于时序的控制）

The description of data flow is as follows: FIFO memory is present in the LCDCDMA. When FIFO is empty or partially empty, the LCDCDMA requests data fetching from the frame memory based on the burst memory transfer mode (consecutive memory fetching of 4 words (16 bytes) per one burst request without allowing the bus mastership to another bus master during the bus transfer). When the transfer request is accepted by bus arbitrator in the memory controller, there will be four successive word data transfers from system memory to internal FIFO. The total size of FIFO is 28 words, which consists of 12 words FIFOL and 16 words FIFOH, respectively. The S3C2440A has two FIFOs to support the dual scan display mode. In case of single scan mode, one of the FIFOs (FIFOH) can only be used.

3.4 TFT LCD CONTROLLER OPERATION

The TIMEGEN generates the control signals for LCD driver, such as VSYNC, HSYNC, VCLK, VDEN, and LEND signal. These control signals are highly related with the configurations on the LCDCON1/2/3/4/5 registers in the REGBANK. Base on these programmable configurations on the LCD control registers in the REGBANK, the TIMEGEN can generate the programmable control signals suitable for the support of many different types of LCD drivers.

TIMEGEN 寄存器产生控制信号，例如：VSYNC、HSYNC、VCLK、VDEN 和 LEND 信号；这些控制信号通过配置 REGBANK 中的 LCDCON1/2/3/4/5 控制寄存器来产生。

The VSYNC signal is asserted to cause the LCD’s line pointer to start over at the top of the display.

VSYNC 信号使得 LCD’s line pointer 跳转显示开头。

The VSYNC and HSYNC pulse generation depends on the configurations of both the HOZVAL field and the LINEVAL field in the LCDCON2/3 registers. The HOZVAL and LINEVAL can be determined by the size of the LCD panel according to the following equations:

— $HOZVAL = (Horizontal display size) -1 $

— $LINEVAL = (Vertical display size) -1 $

VSYNC 和 HSYNC 信号的产生依赖于 HOZVAL 和 LINEVAL。由寄存器 LCDCON2/3 来配置 HOZVAL 和 LINEVAL。

The rate of VCLK signal depends on the CLKVAL field in the LCDCON1 register. Table 15-3 defines the relationship of VCLK and CLKVAL. The minimum value of CLKVAL is 0.

VCLK 信号的产生依赖于 CLKVAL 。由寄存器 LCDCON1 来配置 CLKVAL 的值。

$VCLK(Hz) = HCLK/[(CLKVAL+1)x2] $

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The frame rate is VSYNC signal frequency. The frame rate is related with the field of VSYNC, VBPD, VFPD, LINEVAL, HSYNC, HBPD, HFPD, HOZVAL, and CLKVAL in LCDCON1 and LCDCON2/3/4 registers. Most LCD drivers need their own adequate frame rate. The frame rate is calculated as follows:

帧同步信号 VSYNC 由 VSYNC、VBPD、VFPD、LINEVAL、HSYNC、HBPD、HFPD、HOZVAL、CLKVAL 这些信号共同决定，具体公式如下：

Frame Rate = 1/ [ { (VSPW+1) + (VBPD+1) + (LIINEVAL + 1) + (VFPD+1) } x {(HSPW+1) + (HBPD +1) + (HFPD+1) + (HOZVAL + 1) } x { 2 x ( CLKVAL+1 ) / ( HCLK ) } ]

3.5 VIDEO OPERATION

The TFT LCD controller within the S3C2440A supports 1, 2, 4 or 8 bpp (bit per pixel) palettized color displays and 16 or 24 bpp non-palettized true-color displays.

S3C2440A 支持 1、2、4 或 8 bpp 的调色显示方式 或者是 16或24 bpp 的真彩显示方式。

由于我们的 jz2440 使用的是 16 bpp 的真彩色，因此我们只看 16bpp 的真彩色。

16bpp 显示一个单元为 16 比特。内存中每个字（32比特）存放两个像素的信息。通过设置 HWSWP 的值，可以设置像素按照 “大端” 还是“小端”的方式进行存储。

16BPP 可以设置为 （5:5:5:1）的存放，即 RGB 每个色彩占 16字节中的 5 位，余下 1 位空闲不用。或者是（5:6:5）的存储方式，红、绿、蓝分别占5、6、6个比特。

3.6 VIRTUAL DISPLAY (TFT/STN)

虚拟显示

The S3C2440A supports hardware horizontal or vertical scrolling. If the screen is scrolled, the fields of LCDBASEU and LCDBASEL in LCDSADDR1/2 registers need to be changed (see Figure 15-8), except the values of PAGEWIDTH and OFFSIZE.

S3C2440A 支持硬件水平或者竖直滚动操作。由寄存器 LCDSADDR1/2 中的 LCDBASEU 和 LCDBASEL 来配置。

The video buffer in which the image is stored should be larger than the LCD panel screen in size.

由上面这句话，大概可以猜测出来，如果我们想要显示一张大于屏幕分辨率的图片。那么我们就可以分配一个远大于 LCD 显示所需要的显存空间，在 LCD 只显示出图片的一部分，然后通过滑动的方式实现显示的变化。