Regex in VIM

1) The metacharacters

2)  The greedy qualifiers


3)  The non-greedy qualifiers

4) The ranges

[12345], [^"], [a-z], [-0-9], ...

5) The grouping and backreferences

6) The alternatives

Using "\|" you can combine several expressions into one which matches any of its components. The first one matched will be used.
The thing to remember about VIM alternation that it is not greedy. It won't search for the longest possible match, it will use the first that matched. That means that the order of the items in the alternation is important!


7) The operator precedence


8) The examples

(1) There is a file which contains the following lines, we need do the following:

abc => abc=abc
cde => cde=cde

Solution:
:%s/\(.\+\)/\1=\1/

(2)


在verilog代码编写中,可以使用VIM或GVIM进行配置。以下是一个基本的VIM配置,不包含任何插件相关的设置。这些配置可以用于写verilog代码。请注意,本文不涉及插件配置,也不介绍VIM的基本使用方式和技巧,仅作为基本配置的分享交流。可以在.vimrc文件中添加以下配置: ``` " 将jk映射到ESC nnoremap jk <Esc> " 添加折叠功能,可以使用za打开或关闭折叠 set foldmethod=syntax " 快速生成端口列表(input、output) " 在需要生成端口列表的位置输入:GenPortList,即可生成端口列表 command! -nargs=0 GenPortList call GenPortList() " 端口列表生成函数 function! GenPortList() let input_ports = [] let output_ports = [] " 根据需要修改以下代码,添加输入端口和输出端口的正则表达式 let input_regex = '\<input\>' let output_regex = '\<output\>' " 遍历当前文件,查找输入端口和输出端口 let lines = getline(1, '$') for line in lines if line =~ input_regex let port = substitute(line, input_regex, '', '') let input_ports += [port] elseif line =~ output_regex let port = substitute(line, output_regex, '', '') let output_ports += [port] endif endfor " 输出端口列表 echo 'Input ports:' for port in input_ports echo ' ' . port endfor echo 'Output ports:' for port in output_ports echo ' ' . port endfor endfunction ``` 以上配置可以实现将`jk`映射为`ESC`按键,添加折叠功能,并提供了快速生成端口列表的命令。在需要生成端口列表的位置,输入`:GenPortList`即可生成端口列表。请根据需要修改代码中的正则表达式来匹配输入和输出端口。<span class="em">1</span><span class="em">2</span><span class="em">3</span> #### 引用[.reference_title] - *1* *2* [用GVIM/VIM写Verilog——VIM配置分享](https://blog.csdn.net/qq_41467882/article/details/120274829)[target="_blank" data-report-click={"spm":"1018.2226.3001.9630","extra":{"utm_source":"vip_chatgpt_common_search_pc_result","utm_medium":"distribute.pc_search_result.none-task-cask-2~all~insert_cask~default-1-null.142^v93^chatsearchT3_2"}}] [.reference_item style="max-width: 50%"] - *3* [gvim写verilog环境搭建——将文本编辑器客制化定义为你自己的IDE](https://blog.csdn.net/qq_41467882/article/details/128198815)[target="_blank" data-report-click={"spm":"1018.2226.3001.9630","extra":{"utm_source":"vip_chatgpt_common_search_pc_result","utm_medium":"distribute.pc_search_result.none-task-cask-2~all~insert_cask~default-1-null.142^v93^chatsearchT3_2"}}] [.reference_item style="max-width: 50%"] [ .reference_list ]
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