《Digital Design and Computer Architecture》7.4 多周期CPU（1）

教材学习与翻译：简单的多周期处理器实现
原文来自
Digital Design and Computer Architecture, Second Edition
by David M. Harris, Sarah L. Harris
7.4 MULTICYCLE PROCESSOR

7.4.1 多周期数据通路

我们还是像上次一样，从存储器和结构状态开始设计CPU，如图7.16 。在设计单周期CPU时，指令存储器和数据存储器是分开的，因为指令和数据的读取是在同一个周期中进行的。现在，我们把指令和数据存储器结合起来。这是可以实现的，因为我们可以在一个周期中读取指令，然后在另一个周期中读写数据，同时PC和寄存器中的值保持不变。我们将通过不断添加模块来分析每一条指令的每一步工作，从而逐步搭建数据通路。新添加的连线用黑色线标出（新的控制信号用蓝色标出），已经学过的部分用灰色标出。

Again, we begin our design with the memory and architectural state of the MIPS processor, shown in Figure 7.16. In the single-cycle design, we used separate instruction and data memories because we needed to read the instruction memory and read or write the data memory all in one cycle. Now, we choose to use a combined memory for both instructions and data. This is more realistic, and it is feasible because we can read the instruction in one cycle, then read or write the data in a separate cycle. The PC and register file remain unchanged. We gradually build the datapath by adding components to handle each step of each instruction. The new connections are emphasized in black (or blue, for new control signals), whereas the hardware that has already been studied is shown in gray.

PC存储了当前要执行的指令的地址。指令执行的第一步是将指令从指令存储器中读出来。图7.17展示了：PC直接连接到（指令）存储器的地址输入端口。指令读出后，被存储在一个新的，非结构性的指令寄存器中，供以后的时钟周期使用。指令寄存器接受一个使能信号：IR Write，该信号有效时，寄存器中的值可以被更新。

The PC contains the address of the instruction to execute. The first step is to read this instruction from instruction memory. Figure 7.17 shows that the PC is simply connected to the address input of the instruction memory. The instruction is read and stored in a new nonarchitectural Instruction Register so that it is available for future cycles. The Instruction Register receives an enable signal, called IRWrite, that is asserted when it should be updated with a new instruction.

lw指令通路的实现

就像我们对单周期处理器所做的那样，我们要先建立lw指令的数据通路，然后对其进行补充和优化，使之能够处理其他的指令。
对于lw指令，读出指令后的下一步是读取源寄存器中的基址。这个寄存器的由指令的rs域指出，即Instr[25:21]。指令的这几位连接到寄存器组的一个地址输入：A1，如图7.18。寄存器组读取数据后将数据送到输出端口RD1。这个值被存储在另一个非结构性寄存器A中。

As we did with the single-cycle processor, we will work out the datapath connections for the lw instruction. Then we will enhance the datapath to handle the other instructions.
For a lw instruction, the next step is to read the source register containing the base address. This register is specified in the rs field of the instruction, Instr25:21. These bits of the instruction are connected to one of the address inputs, A1, of the register file, as shown in Figure 7.18. The register file reads the register onto RD1. This value is stored in another nonarchitectural register, A.

lw指令还需要一个偏移量。偏移量由指令的立即数域指出，即Instr[15:0]。偏移量需要符号扩展至32位，如图7.19。经符号扩展后的32位数据记为SignImm。出于一致性考虑，我们也可以将SignImm存储在另一个非结构性寄存器中。然而，SignImm是Instr的组合函数，在处理当前指令时，SignImm的值不会改变，所以我们没有必要为这个不会改变的值分配一个寄存器。

The lw instruction also requires an offset. The offset is stored in the
immediate field of the instruction, Instr15:0, and must be sign-extended to 32 bits, as shown in Figure 7.19. The 32-bit sign-extended value is called SignImm. To be consistent, we might store SignImm in another nonarchitectural register. However, SignImm is a combinational function of Instr and will not change while the current instruction is being processed, so there is no need to dedicate a register to hold the constant value.

要载入的数据的地址是基址和偏移量的和，我们用一个ALU来运算它们的和，如图7.20。为了进行加法运算，ALUControl应设为 010，运算结果ALUResult 存储在一个非结构性寄存器 ALUOut中。

The address of the load is the sum of the base address and offset. We
use an ALU to compute this sum, as shown in Figure 7.20. ALUControl
should be set to 010 to perform an addition. ALUResult is stored in a nonarchitectural register called ALUOut.

接下来我们需要将计算结果接入存储器。我们在存储器的地址输入前设置一个多路选择器来选择存储器地址Adr是来自PC还是ALUOut，如图7.21。该选择器的选择控制信号记为IorD，表示“指令”或“数据”。从存储器中读出的数据存储在另一个非结构性寄存器中，该寄存器记为Data。注意到地址选择器让我们能够在lw指令进行时多次访问存储器。第一次是根据PC值获取指令，第二次是根据ALU输出的地址读取数据。因此，IorD必须在这两个过程中取不同的值。在7.4.2中，我们将设计用于生成这些顺序控制信号的有限状态机。

The next step is to load the data from the calculated address in the memory. We add a multiplexer in front of the memory to choose the memory address, Adr, from either the PC or ALUOut, as shown in Figure 7.21. The multiplexer select signal is called IorD, to indicate either an instruction or data address. The data read from the memory is stored in another nonarchitectural register, called Data. Notice that the address multiplexer permits us to reuse the memory during the lw instruction. On the first step, the address is taken from the PC to fetch the instruction. On a later step, the address is taken from ALUOut to load the data. Hence, IorD must have different values on different steps. In Section 7.4.2, we develop the FSM controller that generates these sequences of control signals.