以CortexR5为例的ARM通用寄存器说明

Platform: Cortex-R5
Architecture: ARMv7-A
Total registers:
(1) 31 general-purpose 32-bit registers
(2) six 32-bit status registers

General-purpose 32-bit registers
(1) Directly accessible registers
a). R0-R12 hold either data or address values.
b). R13 (SP)Stack Pointer
c). R14 (LR)Link Register receive the return address when instruction BL or BLX executed.
d). R15 (PC)Program Counter: reading the address of the current instruction plus (+4 or +8)
(2) No directly accessible registers
a). R16-R30 “caller-saved” or “scratch” registers, which means that they can be used for temporary storage by functions and code without the requirement to preserve their values across function calls.

Status registers
(1) CPSR current program status register which contains condition code flags, status bits, and current mode bits.
(2) others