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实验一
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:17:16 05/18/2022
-- Design Name:
-- Module Name: alu - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity alu is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
INPUT : in STD_LOGIC_VECTOR (15 downto 0);
OUTPUT : out STD_LOGIC_VECTOR (15 downto 0);
stateCnt : out STD_LOGIC_VECTOR (6 downto 0));
end alu;
architecture Behavioral of alu is
signal state: integer range 0 to 4;--记录当前的状态,来判断该进行什么操作
signal temp_A, temp_B, temp_Y : STD_LOGIC_VECTOR (15 downto 0);--定义临时操作数
signal op:STD_LOGIC_VECTOR (3 downto 0);--定义临时操作数
signal Flag_OF : STD_LOGIC;--溢出标志
signal Flag_CF : STD_LOGIC;--进位标志
signal Flag_ZF : STD_LOGIC;--0标志位
signal Flag_SF : STD_LOGIC;--正负标志
signal M: STD_LOGIC:='0';--扩展：对于带符号运算ADC/SBB
begin
process(RST, CLK)
begin
if (RST = '0' )then state <= 0;
temp_A<="0000000000000000";
temp_B<="0000000000000000";
state <= 0;
output <= (others=>'0');
stateCnt <= not "0000000";
elsif CLK'event and CLK = '1' then
case state is
when 0 => state <= 1;
temp_A <= INPUT;
stateCnt <= not "1000000";
OUTPUT<=INPUT;
when 1 => state <= 2;
temp_B <= INPUT;
stateCnt <= not "1111001";
OUTPUT<=INPUT;
when 2 => state <= 3;
op <= INPUT(3 downto 0);
stateCnt <= not "0100100";
OUTPUT <= INPUT;
when 3 => state <= 4;
OUTPUT<= temp_Y;
stateCnt <= not "0110000";
when 4 => state <= 0;
OUTPUT<= "000000000000"& Flag_OF & Flag_CF & Flag_ZF & Flag_SF;
stateCnt <= not "0011001";
end case;
end if;
end process;
process(rst,op)
begin
Flag_OF <= '0';
Flag_CF <= '0';
Flag_ZF <= '0';
Flag_SF <= '0';
M <='0';
CASE op IS
WHEN "0000" => --ADD加
temp_Y <= temp_A + temp_B;
Flag_OF <=(temp_A(15)and temp_B(15) and (not(temp_Y(15)))) or ((not(temp_A(15)))and (not(temp_B(15))) and (temp_Y(15)));
if(temp_A(15)='1' and temp_B(15)='1' and temp_Y(15)='0') then --进行溢出和是否进位判断
Flag_CF <='1';
end if;
if(temp_Y = "0000000000000000") then --0标志位与0进行比较
Flag_ZF <= '1';
end if;
if(temp_Y(15) = '1') then --通过符号位来判断正负标志位
Flag_SF <= '1';
end if;
WHEN "0001" => --SUB减
temp_Y <= temp_A - temp_B;
Flag_OF <=(temp_A(15)and temp_B(15) and (not(temp_Y(15)))) or ((not(temp_A(15)))and (not(temp_B(15))) and (temp_Y(15)));
if(temp_A(15)='0' and temp_B(15)='1') then --进行溢出和是否进位判断
Flag_CF <='1';
end if;
if(temp_Y = "0000000000000000") then --0标志位与0进行比较
Flag_ZF <= '1';
end if;
if(temp_Y(15) = '1') then --通过符号位来判断正负标志位
Flag_SF <= '1';
end if;
WHEN "0010" => --AND逻辑与
temp_Y <= (temp_A AND temp_B);
Flag_OF <= '0';
Flag_CF <= '0';
if(temp_Y = "0000000000000000") then --0标志位与0进行比较
Flag_ZF <= '1';
end if;
if(temp_Y(15) = '1') then --通过符号位来判断正负标志位
Flag_SF <= '1';
end if;
WHEN "0011" => --OR逻辑或
temp_Y <= (temp_A OR temp_B);
Flag_OF <= '0';
Flag_CF <= '0';
if(temp_Y = "0000000000000000") then --0标志位与0进行比较
Flag_ZF <= '1';
end if;
if(temp_Y(15) = '1') then --通过符号位来判断正负标志位
Flag_SF <= '1';
end if;
WHEN "0100" => --XOR逻辑异或
temp_Y <= (temp_A XOR temp_B);
Flag_OF <= '0';
Flag_CF <= '0';
if(temp_Y = "0000000000000000") then --0标志位与0进行比较
Flag_ZF <= '1';
end if;
if(temp_Y(15) = '1') then --通过符号位来判断正负标志位
Flag_SF <= '1';
end if;
WHEN "0101" => --NOT逻辑非
temp_Y <= NOT temp_A ;
Flag_OF <= '0';
Flag_CF <= '0';
if(temp_Y = "0000000000000000") then --0标志位与0进行比较
Flag_ZF <= '1';
end if;
if(temp_Y(15) = '1') then --通过符号位来判断正负标志位
Flag_SF <= '1';
end if;
WHEN "0110" => --SLL逻辑左移
temp_Y <= temp_A;
temp_Y <= to_stdlogicvector( to_bitvector(temp_Y) SLL conv_integer(temp_B));
Flag_OF <= '0';
Flag_CF <= '0';
if(temp_Y = "0000000000000000") then --0标志位与0进行比较
Flag_ZF <= '1';
end if;
if(temp_Y(15) = '1') then --通过符号位来判断正负标志位
Flag_SF <= '1';
end if;
WHEN "0111" => --SLA算术左移
temp_Y <= temp_A;
temp_Y <= to_stdlogicvector( to_bitvector(temp_Y) SLA conv_integer(temp_B));
Flag_OF <= '0';
Flag_CF <= '0';
if(temp_Y = "0000000000000000") then --0标志位与0进行比较
Flag_ZF <= '1';
end if;
if(temp_Y(15) = '1') then --通过符号位来判断正负标志位
Flag_SF <= '1';
end if;
WHEN "1000" => --SRL逻辑右移
temp_Y <= temp_A;
temp_Y <= to_stdlogicvector( to_bitvector(temp_Y) SRL conv_integer(temp_B));
Flag_OF <= '0';
Flag_CF <= '0';
if(temp_Y = "0000000000000000") then --0标志位与0进行比较
Flag_ZF <= '1';
end if;
if(temp_Y(15) = '1') then --通过符号位来判断正负标志位
Flag_SF <= '1';
end if;
WHEN "1001" => --SRA算术右移
temp_Y <= temp_A;
temp_Y <= to_stdlogicvector( to_bitvector(temp_Y) SRA conv_integer(temp_B));
Flag_OF <= '0';
Flag_CF <= '0';
if(temp_Y = "0000000000000000") then --0标志位与0进行比较
Flag_ZF <= '1';
end if;
if(temp_Y(15) = '1') then --通过符号位来判断正负标志位
Flag_SF <= '1';
end if;
WHEN "1010" => --ROL循环逻辑左移
temp_Y <= temp_A;
temp_Y <= to_stdlogicvector( to_bitvector(temp_Y) ROL conv_integer(temp_B));
Flag_OF <= '0';
Flag_CF <= '0';
if(temp_Y = "0000000000000000") then --0标志位与0进行比较
Flag_ZF <= '1';
end if;
if(temp_Y(15) = '1') then --通过符号位来判断正负标志位
Flag_SF <= '1';
end if;
WHEN "1011" => --ROR循环逻辑左移
temp_Y <= temp_A;
temp_Y <= to_stdlogicvector( to_bitvector(temp_Y) ROR conv_integer(temp_B));
Flag_OF <= '0';
Flag_CF <= '0';
if(temp_Y = "0000000000000000") then --0标志位与0进行比较
Flag_ZF <= '1';
end if;
if(temp_Y(15) = '1') then --通过符号位来判断正负标志位
Flag_SF <= '1';
end if;
WHEN "1100" => --ADC带进位加法
temp_Y <= temp_A + temp_B + Flag_CF;
Flag_OF <=(temp_A(15)and temp_B(15) and (not(temp_Y(15)))) or ((not(temp_A(15)))and (not(temp_B(15))) and (temp_Y(15)));
if(temp_A(15)='1' and temp_B(15)='1' and temp_Y(15)='0') then --进行溢出和是否进位判断
Flag_CF <='1';
end if;
if(temp_Y = "0000000000000000") then --0标志位与0进行比较
Flag_ZF <= '1';
end if;
if(temp_Y(15) = '1') then --通过符号位来判断正负标志位
Flag_SF <= '1';
end if;
WHEN "1101" => --SBB带进位减法
temp_Y <= temp_A - temp_B - Flag_CF;
Flag_OF <=(temp_A(15)and temp_B(15) and (not(temp_Y(15)))) or ((not(temp_A(15)))and (not(temp_B(15))) and (temp_Y(15)));
if(temp_A(15)='0' and temp_B(15)='1') then --进行溢出和是否进位判断
Flag_CF <='1';
end if;
if(temp_Y = "0000000000000000") then --0标志位与0进行比较
Flag_ZF <= '1';
end if;
if(temp_Y(15) = '1') then --通过符号位来判断正负标志位
Flag_SF <= '1';
end if;
WHEN OTHERS=>
temp_Y <= "1111111111111111";--默认报错用-1
end case;
end process;
end Behavioral;
实验二
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:45:14 05/22/2022
-- Design Name:
-- Module Name: Sram - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Sram is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
DATA : inout STD_LOGIC_VECTOR (15 downto 0);
ADDR : out STD_LOGIC_VECTOR (15 downto 0);
Input_data : in STD_LOGIC_VECTOR (15 downto 0);
RAM1_EN : out STD_LOGIC;--片选信号 RAM1使能
RAM1_OE : out STD_LOGIC;--读信号 输出使能
RAM1_WE : out STD_LOGIC;--写信号 写使能
ctrl_r : in STD_LOGIC;
dbc : out STD_LOGIC;
LIGHT : out STD_LOGIC_VECTOR (15 downto 0);
stateCnt: out STD_LOGIC_VECTOR (6 downto 0);--对应七段数码管);
stateCnt2: out STD_LOGIC_VECTOR (6 downto 0));--对应七段数码管);
end Sram;
architecture Behavioral of Sram is
signal tmp_addr:STD_LOGIC_VECTOR (15 downto 0):=x"0000"; --X代表16进制:X"0000"等于"0000000000000000"
signal tmp_read_addr:STD_LOGIC_VECTOR (15 downto 0):=x"0000";
signal tmp_data:STD_LOGIC_VECTOR (15 downto 0):=x"0000";
signal tmp_read_data:STD_LOGIC_VECTOR (15 downto 0):=x"0000";
signal to_light:STD_LOGIC_VECTOR (15 downto 0):=x"0000";
type sram_state is(prepare,start,achieve,waiting,over);--枚举类型 定义SRAM状态 写状态
--type read_sram_state is (waiting,start,reading,over);--读取状态
type prj_state is(r,w,n);--枚举类型
signal ctrl_state:prj_state;--枚举类型赋给ctrl_state
signal write_state,read_state:sram_state;
--signal read_state:read_sram_state;
signal state_controler:std_logic_vector(1 downto 0):="00";
begin
process(RST,ctrl_r)
begin
if RST='0' then
ctrl_state <=N; --仅当重置时状态才为N
stateCnt2 <= not "0000000";
elsif rising_edge(ctrl_r) then
case ctrl_state is
when N =>
stateCnt2 <= not "1111001";
ctrl_state<=W; --重置后开始先写入
when W =>
stateCnt2 <= not "0100100";
ctrl_state<=R; --写后开始读
when R =>
stateCnt2 <= not "1111001";
ctrl_state<=W; --读完再写
end case;
end if;
end process;
process(RST,CLK,ctrl_state)
begin
if RST='0' then --重置
tmp_data <=x"0000";
tmp_read_addr <=x"0000";
tmp_addr <=x"0000"; --x表示八进制（应该是十六进制）
to_light <=x"0000";
RAM1_EN <= '1'; --RAM1的片选信号1未选中
RAM1_OE <= '0'; --读信号
RAM1_WE <= '0'; --写信号
write_state <= waiting;
read_state <= waiting;
stateCnt <= not "0000000";
elsif rising_edge(CLK) then --clk上升沿
case ctrl_state is
when N => --仅当重置时状态才为N，当重置时不需有任何其他操作
when W =>
case write_state is
when waiting => --0
write_state <= prepare;
read_state <=waiting;
tmp_addr <= INPUT_data;
stateCnt <= not"1000000";
when prepare => --1
tmp_data<=Input_data;
RAM1_EN <= '0';
RAM1_OE <= '1';
RAM1_WE <= '1';
ADDR <= tmp_addr;
DATA <= tmp_data;
write_state <= start;
stateCnt <= not"1111001";
when start => --2
ADDR <= tmp_addr;
DATA <= tmp_data;
RAM1_WE<='0';
RAM1_OE<='1';
write_state <= achieve;
stateCnt <= not"0100100";
when achieve=> --3
RAM1_OE<='1';
RAM1_WE<='0';
to_light<=DATA;
write_state<=over;
stateCnt <= not"0110000";
when over=> --4
write_state<=waiting;
tmp_addr<=tmp_addr + 1;
stateCnt <= not"0011001";
end case;
when R=>
case read_state is
when waiting => --0
read_state<=prepare;
write_state<=waiting;
stateCnt <= not"1000000";
when prepare=> --1
tmp_read_addr<=Input_data;--输入读取的地址位置
RAM1_EN<='0';
RAM1_OE<='1';
RAM1_WE<='1';
ADDR<=tmp_read_addr;
DATA<=(others=>'Z');
read_state<=start;
stateCnt <= not"1111001";
when start=> --2
RAM1_OE<='0';
RAM1_WE<='1';
ADDR<=tmp_read_addr;
read_state<=achieve;
stateCnt <= not"0100100";
when achieve=> --3
RAM1_OE<='0';
RAM1_WE<='1';
to_light<=DATA;
read_state<=over;
stateCnt <= not"0110000";
when over=> --4
read_state<=waiting;
tmp_read_addr<=tmp_read_addr + 1;
stateCnt <= not"0011001";
end case;
end case;
end if;
dbc<='1';
end process;
light<=to_light;
end Behavioral;
实验四
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:09:39 05/17/2023
-- Design Name:
-- Module Name: cpu1 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity cpu is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
input : in STD_LOGIC_VECTOR (15 downto 0);
output : out STD_LOGIC_VECTOR (15 downto 0);
seg : out STD_LOGIC_VECTOR (13 downto 0);
ram_en : out STD_LOGIC; --使能端
ram_oe : out STD_LOGIC; --读
ram_rw : out STD_LOGIC; --写
ram_addr : out STD_LOGIC_VECTOR (17 downto 0);
DBC :OUT STD_LOGIC;
ram_data : inout STD_LOGIC_VECTOR (15 downto 0));
end cpu;
architecture Behavioral of cpu is
signal state:STD_LOGIC_VECTOR (3 downto 0):="0000";--指令流程五个工作周期
signal r0:STD_LOGIC_VECTOR (15 downto 0):="0000000000000000";--通用寄存器
signal r1:STD_LOGIC_VECTOR (15 downto 0):="0000000000000001";
signal r2:STD_LOGIC_VECTOR (15 downto 0):="0000000000000010";
signal r3:STD_LOGIC_VECTOR (15 downto 0):="0000000000000011";
signal r4:STD_LOGIC_VECTOR (15 downto 0):="0000000000000100";
signal r5:STD_LOGIC_VECTOR (15 downto 0):="0000000000000101";
signal r6:STD_LOGIC_VECTOR (15 downto 0):="0000000000000110";
signal r7:STD_LOGIC_VECTOR (15 downto 0):="0000000000000111";
signal ir:STD_LOGIC_VECTOR (15 downto 0):="0000000000000000";--指令寄存器
signal pc:STD_LOGIC_VECTOR (15 downto 0):="0000000000010000";--程序计数器
procedure rr(a:in STD_LOGIC_VECTOR (2 downto 0);b:out STD_LOGIC_VECTOR (15 downto 0)) is--寄存器取值
begin
case a is
when "000"=>b:=r0;
when "001"=>b:=r1;
when "010"=>b:=r2;
when "011"=>b:=r3;
when "100"=>b:=r4;
when "101"=>b:=r5;
when "110"=>b:=r6;
when "111"=>b:=r7;
when others=>b:="0000000000000000";
end case;
end rr;
begin
process (clk,rst)
variable mar:STD_LOGIC_VECTOR (15 downto 0):="0000000000010000";--访存地址
variable mbr:STD_LOGIC_VECTOR (15 downto 0):="0000000000000000";
variable op:STD_LOGIC_VECTOR (4 downto 0):="00000";--操作码
variable rx,ry,RZ:STD_LOGIC_VECTOR (2 downto 0):="000";--访问的寄存器
variable imme:STD_LOGIC_VECTOR (15 downto 0):="0000000000000000";--立即数
variable t1,t2,t3:STD_LOGIC_VECTOR (15 downto 0):="0000000000000000";--临时量
begin
if (rst='0') then
state<="0000";
output<="0000000000000000";
mar:="0000000000010000";
pc<="0000000000010000";
elsif (CLK'event and CLK = '0') then
case state is
when "0000"=>--初始状态
DBC<='1';
case input(2 downto 0) is
when"001"=> state<="0001";
DBC<='1';
when"011"=> state<="0011";
DBC<='1';
ram_data<="ZZZZZZZZZZZZZZZZ";
when others =>
end case;
output<=input;
when "0001"=> --向主存写入数据和指令
output<=input;
DBC<='1';
ram_addr<="00"&input;
ram_en<='0';
ram_oe<='1';
ram_rw<='1';
state<="0010";
when"0010"=>
DBC<='1';
ram_data<=input;
output<=input;
ram_en<='0';
ram_oe<='1';
ram_rw<='0';
state<="0001";
when "0011"=>--取指阶段
DBC<='1';
state<="1111";
ram_addr<="00"&MAR;
ram_data<="ZZZZZZZZZZZZZZZZ";
output<=mar;-- 输出指令地址
ram_en<='0';
ram_oe<='0';
ram_rw<='1';
WHEN "1111" =>
DBC<='1';
ram_en<='0';
ram_oe<='1';
ram_rw<='1';
state<="0100";
ir<=ram_data;
pc<=pc+1;
--ram_en<='1';
--ram_oe<='1';
--ram_rw<='1';
when "0100"=>--译码阶段
DBC<='1';
ram_en<='0';
ram_oe<='1';
ram_rw<='1';
state<="0101";
output<=ir; --输出指令
op:=ir(15 downto 11);
case op is
when "01111"=>
DBC<='1'; --MOVE
rx:=ir(10 downto 8);
ry:=ir(7 downto 5);
--imme:="00000000"&ir(7 downto 0);
--mar:=imme;
when "11100"=>
DBC<='1'; --ADDU
rx:=ir(10 downto 8);
--imme:="00000000"&ir(7 downto 0);
ry:=ir(7 downto 5);
rz:=ir(4 downto 2);
--SUBU
when "00100"=> --BEQZ
DBC<='1';
rx:=ir(10 downto 8);
imme:="00000000"&ir(7 downto 0);
when "10011"=> --LW
DBC<='1';
rx:=ir(10 downto 8);
ry:=ir(7 downto 5);
imme:="00000000000"&ir(4 downto 0);
rr(rx,t1);
mar:=t1+imme;
when "11101"=> --XOR
DBC<='1';
rx:=ir(10 downto 8);
ry:=ir(7 downto 5);
when "11011"=> --SW
DBC<='1';
rx:=ir(10 downto 8);
ry:=ir(7 downto 5);
imme:="00000000000"&ir(4 downto 0);
rr(rx,t1);
rr(ry,t2);
mar:=t1+imme;
when others=>
end case;
when "0101"=>--执行阶段
DBC<='1';
state<="0110";
output<=ir;
case op is
when "11100"=> --ADDU
if(ir(1 downto 0)= "01") then
rr(rx,t1);
rr(ry,t2);
t3:=t1+t2;
elsif(ir(1 downto 0)= "11") then --SUBU
rr(rx,t1);
rr(ry,t2);
t3:=t1-t2;
else null;
end if;
when "00100"=> --BNEZ
DBC<='1';
rr(rx,t1);
if ( t1="0000000000000000") then
pc<=MAR+imme;
end if;
when "10011"=> --LW
DBC<='1';
ram_addr<="00"&mar;
when "11101"=> --XOR
DBC<='1';
if(ir(4 downto 0)= "01110") then
rr(rx,t1);
rr(ry,t2);
t3:=t1 xor t2;
elsif(ir(4 downto 0)= "01101") then -- OR
rr(rx,t1);
rr(ry,t2);
t3:=t1 or t2;
else null;
end if;
when "11011"=> --SW
DBC<='1';
ram_addr<="00"&MAR;
mbr:=t2;
when "01111"=> --MOVE
DBC<='1';
rr(ry,t2);
t3:=t2;
--ram_en<='0';
--ram_oe<='0';
--ram_rw<='1';
--ram_addr<="00"&mar;
--mbr:=ram_data;
when others=>
end case;
when "0110"=>--访存阶段
state<="0111";
case op is
when "10011"=>--lw
ram_en<='0';
ram_oe<='0';
ram_rw<='1';
ram_data<="ZZZZZZZZZZZZZZZZ";
mbr:=ram_data;
--output<=MAR(7 downto 0)&mbr(7 downto 0);
when "11011"=>--sw
ram_data<=mbr;
ram_en<='0';
ram_oe<='1';
ram_rw<='0';
output<=MAR(7 downto 0)&mbr(7 downto 0);
when others=>output<=ir;
end case;
when "0111"=>--写回阶段
state<="0011";
mar:=pc;
ram_en<='0';
ram_oe<='1';
ram_rw<='1';
case op is
when "11100"=> --ADDIU 和 SUBU
OUTPUT<=T3;
case rz is
when "000"=>r0<=t3;
when "001"=>r1<=t3;
when "010"=>r2<=t3;
when "011"=>r3<=t3;
when "100"=>r4<=t3;
when "101"=>r5<=t3;
when "110"=>r6<=t3;
when "111"=>r7<=t3;
when others=>
end case;
when "10011"=>--LW
--OUTPUT<=MAR(7 downto 0)&mbr(7 downto 0);
case ry is
when "000"=>r0<=mbr;
when "001"=>r1<=mbr;
when "010"=>r2<=mbr;
when "011"=>r3<=mbr;
when "100"=>r4<=mbr;
when "101"=>r5<=mbr;
when "110"=>r6<=mbr;
when "111"=>r7<=mbr;
when others=>
end case;
when "01111" => --move
output<=t3;
case rx is
when "000"=>r0<=t3;
when "001"=>r1<=t3;
when "010"=>r2<=t3;
when "011"=>r3<=t3;
when "100"=>r4<=t3;
when "101"=>r5<=t3;
when "110"=>r6<=t3;
when "111"=>r7<=t3;
when others=>
end case;
when "11101"=>-- XOR AND OR
output<=t3;
case rx is
when "000"=>r0<=t3;
when "001"=>r1<=t3;
when "010"=>r2<=t3;
when "011"=>r3<=t3;
when "100"=>r4<=t3;
when "101"=>r5<=t3;
when "110"=>r6<=t3;
when "111"=>r7<=t3;
when others=>
end case;
when others=>
end case;
when others=>
state<="0000";
end case;
end if;
end process;
process (state)
begin
case state is
when "0000"=>seg<="01111110111111"; --00
when "0001"=>seg<="01111110100001"; --01
when "0010"=>seg<="01111111011011"; --02
when "0011"=>seg<="01000010100001"; --11
when "0100"=>seg<="01000011011011"; --12
when "0101"=>seg<="01000011110011"; --13
when "0110"=>seg<="01000011100101"; --14
when "0111"=>seg<="01000011110110"; --15
when "1111"=>seg<="01000010100001";
when others=>
NULL;
end case;
end process;
end Behavioral;引脚记得自己找老师要然后加上。
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