msm8953之串口dts配置

https://blog.csdn.net/xuecz1230/article/details/78672662

msm8953支持4路串口，编号uart2、uart4、uart5、uart6

基地址：

中断号：

dts配置如下;

xxx .dtsi

 

1. &blsp1_uart0 {//uart2

2. status = "ok";

3. pinctrl-names = "default";

4. pinctrl-0 = <&uart_console_active>;

5. };

6. &blsp1_uart4 {//uart4

7. status = "ok";

8. pinctrl-names = "default";

9. pinctrl-0 = <&uart4_console_active>;

10. };

11.  

12. &blsp2_uart5 {//uart5

13. status = "ok";

14. pinctrl-names = "default";

15. pinctrl-0 = <&uart5_console_active>;

16. };

17.  

18. &blsp2_uart6 {//uart6

19. status = "ok";

20. pinctrl-names = "default";

21. pinctrl-0 = <&uart6_console_active>;

22. };

xxx-msm8953.dtsi

 

1. blsp1_uart0: serial@78af000 {//uart2

2. compatible = "qcom,msm-lsuart-v14";

3. reg = <0x78af000 0x200>;

4. interrupts = <0 107 0>;

5. status = "disabled";

6. clocks = <&clock_gcc clk_gcc_blsp1_uart1_apps_clk>,

7. <&clock_gcc clk_gcc_blsp1_ahb_clk>;

8. clock-names = "core_clk", "iface_clk";

9. };

10.  

11. blsp1_uart4:serial@78b0000 {//uart4

12. compatible = "qcom,msm-lsuart-v14";

13. reg = <0x78b0000 0x200>;

14. interrupts = <0 108 0>;

15. status = "disabled";

16. clocks = <&clock_gcc clk_gcc_blsp1_uart2_apps_clk>,

17. <&clock_gcc clk_gcc_blsp1_ahb_clk>;

18. clock-names = "core_clk", "iface_clk";

19. };

20.  

21. blsp2_uart5:serial@7aef000 {//uart5

22. compatible = "qcom,msm-lsuart-v14";

23. reg = <0x7aef000 0x200>;

24. interrupts = <0 306 0>;

25. status = "disabled";

26. clocks = <&clock_gcc clk_gcc_blsp2_uart1_apps_clk>,

27. <&clock_gcc clk_gcc_blsp2_ahb_clk>;

28. clock-names = "core_clk","iface_clk";

29. };

30.  

31. blsp2_uart6:serial@7af0000 {//uart6

32. compatible = "qcom,msm-lsuart-v14";

33. reg = <0x7af0000 0x200>;

34. interrupts = <0 307 0>;

35. status = "disabled";

36. clocks = <&clock_gcc clk_gcc_blsp2_uart2_apps_clk>,

37. <&clock_gcc clk_gcc_blsp2_ahb_clk>;

38. clock-names = "core_clk","iface_clk";

39. };

 

 

xxx-msm8953-pinctrl.dtsi

 

1. pmx-uartconsole {//uart2

2. uart_console_active: uart_console_active {

3. mux {

4. pins = "gpio4", "gpio5";

5. function = "blsp_uart2";

6. };

7.  

8. config {

9. pins = "gpio4", "gpio5";

10. drive-strength = <2>;

11. bias-disable;

12. };

13. };

14. uart_console_sleep: uart_console_sleep {

15. mux {

16. pins = "gpio4", "gpio5";

17. function = "blsp_uart2";

18. };

19.  

20. config {

21. pins = "gpio4", "gpio5";

22. drive-strength = <2>;

23. bias-pull-down;

24. };

25. };

26.  

27. };

28.  

29. pmx-uart4console {//uart4

30. uart4_console_active: uart4_console_active {

31. mux {

32. pins = "gpio12","gpio13";

33. function = "blsp_uart4";

34. };

35. config {

36. pins = "gpio12","gpio13";

37. drive-strength = <2>;

38. bias-disable;

39. };

40. };

41. uart4_console_sleep: uart4_console_sleep {

42. mux {

43. pins = "gpio12","gpio13";

44. function = "blsp_uart4";

45. };

46. config {

47. pins = "gpio12","gpio13";

48. drive-strength = <2>;

49. bias-pull-down;

50. };

51. };

52. };

53.  

54. pmx-uart5console {//uart5

55. uart5_console_active: uart_console_active {

56. mux {

57. pins = "gpio16","gpio17";

58. function = "blsp_uart5";

59. };

60.  

61. config {

62. pins = "gpio16","gpio17";

63. drive-strength = <2>;

64. bias-disable;

65. };

66. };

67. uart5_console_sleep: uart5_console_sleep {

68. mux {

69. pins = "gpio16","gpio17";

70. function = "blsp_uart5";

71. };

72.  

73. config {

74. pins = "gpio16","gpio17";

75. drive-strength = <2>;

76. bias-disable;

77. };

78. };

79.  

80. };

81.  

82. pmx-uart6console {//uart6

83. uart6_console_active: uart_console_active {

84. mux {

85. pins = "gpio20","gpio21";

86. function = "blsp_uart6";

87. };

88.  

89. config {

90. pins = "gpio20","gpio21";

91. drive-strength = <2>;

92. bias-disable;

93. };

94. };

95. uart6_console_sleep: uart6_console_sleep {

96. mux {

97. pins = "gpio20","gpio21";

98. function = "blsp_uart6";

99. };

100.  

101. config {

102. pins = "gpio20","gpio21";

103. drive-strength = <2>;

104. bias-disable;

105. };

106. };

107. };