[s3c2416x移植u-boot-2015.10] 让u-boot-2015.10支持spl nand的启动

1.先在make menuconfig的时候，添加spl的编译选项

1.make menuconfig
    Boot images--->
        SUPPORT SPL--->
            [*]Enable SPL（new）


2.保存退出
3.make ARCH=arm CROSS_COMPILE=arm-none-linux-gnueabi-
4.编译会生成spl文件，其下会有u-boot-spl.bin

此时，生成的u-boot-spl.bin其实并没有什么卵用，它是不能引导我们的设备启动，因而需要对其加以修改，使它支持。

*注意，我们需要的bin文件是u-boot.bin 和 u-boot-spl.bin。

2.增加nand spl的启动文件

2.1 u-boot-spl.bin应该做的几件事：

• 1.初始化我们的系统时钟，关闭看门狗，关闭所有的中断
• 2.配置系统用的GPIO(可以不选)
• 3.初始化nand
• 4.初始化主存(内存,SDRAM之类)
• 5.拷贝u-boot.bin到SDRAM中，并跳SDRAM中去运行u-boot.bin。

清楚了要做的事之后，我们来手动修改，让我们的u-boot-2015.10满足支持nand-spl的启动方式。

2.2 修改strart.S

start.S是u-boot.bin的开始，也是u-boot-spl.bin的入口，所有，要对其中可能存在的初始化过程，加以避免，使用宏定义的方式，是个不错的选择，比如下面这样：

#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_CPU_S3C2416)
    .../* 这里存放要区分的内容 */
#endif

start.S源文件：

/*
 *  armboot - Startup Code for ARM926EJS CPU-core
 *
 *  Copyright (c) 2003  Texas Instruments
 *
 *  ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
 *
 *  Copyright (c) 2001  Marius Gröger <mag@sysgo.de>
 *  Copyright (c) 2002  Alex Züpke <azu@sysgo.de>
 *  Copyright (c) 2002  Gary Jennejohn <garyj@denx.de>
 *  Copyright (c) 2003  Richard Woodruff <r-woodruff2@ti.com>
 *  Copyright (c) 2003  Kshitij <kshitij@ti.com>
 *  Copyright (c) 2010  Albert Aribaud <albert.u.boot@aribaud.net>
 *
 * SPDX-License-Identifier: GPL-2.0+
 */

#include <asm-offsets.h>
#include <config.h>
#include <common.h>

/*
 *************************************************************************
 *
 * Startup Code (reset vector)
 *
 * do important init only if we don't start from memory!
 * setup Memory and board specific bits prior to relocation.
 * relocate armboot to ram
 * setup stack
 *
 *************************************************************************
 */

    .globl  reset

reset:
    /*
     * set the cpu to SVC32 mode
     */
    mrs r0,cpsr
    bic r0,r0,#0x1f
    orr r0,r0,#0xd3
    msr cpsr,r0

    /*
     * we do sys-critical inits only at reboot,
     * not when booting from ram!
     */
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
    bl  cpu_init_crit
#endif

    bl  _main

/*------------------------------------------------------------------------------*/

    .globl  c_runtime_cpu_setup
c_runtime_cpu_setup:

    bx  lr

/*
 *************************************************************************
 *
 * CPU_init_critical registers
 *
 * setup important registers
 * setup memory timing
 *
 *************************************************************************
 */
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
cpu_init_crit:
    /*
     * flush D cache before disabling it
     */
    mov r0, #0
flush_dcache:
    mrc p15, 0, r15, c7, c10, 3
    bne flush_dcache

    mcr p15, 0, r0, c8, c7, 0   /* clear TLB Part */
    mcr p15, 0, r0, c7, c5, 0   /* clear I Cache Part */

    /*
     * disable MMU and D cache
     * enable I cache if CONFIG_SYS_ICACHE_OFF is not defined
     */
    mrc p15, 0, r0, c1, c0, 0

    /* clear c1's bit9,bit8*/
    bic r0, r0, #0x00000300

    /* clear c1's bit7(0:litile endi) bit2(0:Dcache disable) bit0(0:MMU disable)*/
    bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */

#ifdef CONFIG_SYS_EXCEPTION_VECTORS_HIGH
    orr r0, r0, #0x00002000 /* set bit 13 (--V- ----) */
#else
    bic r0, r0, #0x00002000 /* clear bit 13 (--V- ----) */
#endif

    orr r0, r0, #0x00000002 /* set bit 2 (A) Align */
#ifndef CONFIG_SYS_ICACHE_OFF
    orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
#endif

    mcr p15, 0, r0, c1, c0, 0

    /*
     * Go setup Memory and board specific bits prior to relocation.
     */
    mov ip, lr      /* perserve link reg across call */
    bl  lowlevel_init   /* go setup pll,mux,memory */
    mov lr, ip      /* restore link */
    mov pc, lr      /* back to my caller */
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ 

start.S修改后的文件：

/*
 *  armboot - Startup Code for ARM926EJS CPU-core
 *
 *  Copyright (c) 2003  Texas Instruments
 *
 *  ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
 *
 *  Copyright (c) 2001  Marius Gröger <mag@sysgo.de>
 *  Copyright (c) 2002  Alex Züpke <azu@sysgo.de>
 *  Copyright (c) 2002  Gary Jennejohn <garyj@denx.de>
 *  Copyright (c) 2003  Richard Woodruff <r-woodruff2@ti.com>
 *  Copyright (c) 2003  Kshitij <kshitij@ti.com>
 *  Copyright (c) 2010  Albert Aribaud <albert.u.boot@aribaud.net>
 *
 * SPDX-License-Identifier: GPL-2.0+
 */

#include <asm-offsets.h>
#include <config.h>
#include <common.h>

/*
 *************************************************************************
 *
 * Startup Code (reset vector)
 *
 * do important init only if we don't start from memory!
 * setup Memory and board specific bits prior to relocation.
 * relocate armboot to ram
 * setup stack
 *
 *************************************************************************
 */

    .globl  reset

reset:
    /*
     * set the cpu to SVC32 mode
     */
    mrs r0,cpsr
    bic r0,r0,#0x1f
    orr r0,r0,#0xd3
    msr cpsr,r0

#if defined(CONFIG_S3C2416) && defined(CONFIG_SPL_BUILD)
    /* disable watchdog */
    ldr r0, =0x53000000
    mov r1, =0x0
    str r1, [r0]

    /* disable all IRQ */
    ldr r0, =0x4a000008
    ldr r1, =0xffffffff
    str r1, [r0]
    str r1, [r0, #0x40]

    /* MPLLCON enable  Fout=800MHZ */
    ldr r0, =0x4c000010
    ldr r1, =0x640061
    str r1, [r0]

    /* EPLLCON disable */
    ldr r0, =0x4c000018
    ldr r1, =0x1200102
    str r1, [r0]

    /* LOCKCON0 */
    ldr r0, =0x4c000000
    ldr r1, =0x0FFFF
    str r1, [r0]

    /* LOCKCON1 */
    ldr r0, =0x4c000004
    ldr r1, =0x0FFFF
    str r1, [r0]

    /* CLKDIV0 : Fclk=800MHZ ARMCLK=400MHZ HCLK=133MHZ SSCLK=26M6HZ PCLK=66MHZ */
    ldr r0, =0x4c000030
    ldr r1, =0x22d
    str r1, [r0] 

    /* red led on */
    ldr r0, =0x56000010
    ldr r1, =0x55
    str r1, [r0]
    ldr r1, =0x3f0
    str r1, [r0, #4]

#endif  

    /*
     * we do sys-critical inits only at reboot,
     * not when booting from ram!
     */
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
    bl  cpu_init_crit
#endif

    bl  _main

/*------------------------------------------------------------------------------*/

    .globl  c_runtime_cpu_setup
c_runtime_cpu_setup:

    bx  lr

/*
 *************************************************************************
 *
 * CPU_init_critical registers
 *
 * setup important registers
 * setup memory timing
 *
 *************************************************************************
 */
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
cpu_init_crit:
    /*
     * flush D cache before disabling it
     */
    mov r0, #0
flush_dcache:
    mrc p15, 0, r15, c7, c10, 3
    bne flush_dcache

    mcr p15, 0, r0, c8, c7, 0   /* clear TLB Part */
    mcr p15, 0, r0, c7, c5, 0   /* clear I Cache Part */

    /*
     * disable MMU and D cache
     * enable I cache if CONFIG_SYS_ICACHE_OFF is not defined
     */
    mrc p15, 0, r0, c1, c0, 0

    /* clear c1's bit9,bit8*/
    bic r0, r0, #0x00000300

    /* clear c1's bit7(0:litile endi) bit2(0:Dcache disable) bit0(0:MMU disable)*/
    bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */

#ifdef CONFIG_SYS_EXCEPTION_VECTORS_HIGH
    orr r0, r0, #0x00002000 /* set bit 13 (--V- ----) */
#else
    bic r0, r0, #0x00002000 /* clear bit 13 (--V- ----) */
#endif

    orr r0, r0, #0x00000002 /* set bit 2 (A) Align */
#ifndef CONFIG_SYS_ICACHE_OFF
    orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
#endif

    mcr p15, 0, r0, c1, c0, 0

    /*
     * Go setup Memory and board specific bits prior to relocation.
     */
    mov ip, lr      /* perserve link reg across call */
    bl  lowlevel_init   /* go setup pll,mux,memory */
    mov lr, ip      /* restore link */
    mov pc, lr      /* back to my caller */
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ 

#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_S3C2416)
nand_init:

    /* GPACON config */
    ldr r0, =0x56000000
    ldr r1, =0x7fffff
    str r1, [r0]

    /* GPMCON config */
    ldr r0, =0x56000100
    ldr r1, =0x8
    str r1, [r0]

    /* NFCFG config */
    ldr r0, =0x4e000000
    ldr r1, =0x7772
    str r1, [r0]

    mov pc, lr 


mDDR_init:  


    mov pc, lr

#endif /* CONFIG_SPL_BUILD && CONFIG_S3C2416  */