Verification Topics

Topic1:  Verification flow

Topic2:  How to build Verification Specification?

Topic3:  How to build Verification Objective?

Topic4:  SystemVerilog knowledge

Topic5:  Assertion Based Verification

Topic6:  Coverage Driven Verification

Topic7:  UVM basic knowledge

Topic8:  UVM register verification knowledge and flow

Topic9:  UVM block level ENV and auto-generation

Topic10:  How to build functional coverage?

Topic11:  Block Level Regression Tips

Topic12:  Collect and analysis coverage result

Topic13:  Verification Report Document

Topic14:  Verification Tools Usage discussion

To Be Continued