FPGA笔记

入门阶段

1.

Error: 

Can't launch the ModelSim-Altera software -- the path to the location of the executables for the ModelSim-Altera software were not specified or the executables were not found at specified path.

解决方法：

Tools -> Options -> General -> EDA Tool Options

2.激励信号和被测试模块端口连接部分如果写错，仿真时会提示

# Error: Error loading design 
#        Pausing macro execution

3.如果在两个always块中给同一个reg变量赋值，则会出现multiple driver的错误。

4.在给模块分配引脚时，如果想取消已经分配的引脚，单击选中，再按delete键即可。

5.D触发器组移位时要注意在前面的是旧值。

6.Error (10110): Verilog HDL error at code_led.v(21): variable "data_send" has mixed blocking and nonblocking Procedural Assignments -- must be all blocking or all nonblocking assignments

错误原因：对变量data_send既做非阻塞赋值又做阻塞赋值，这是不允许的。

7.Error (10170): Verilog HDL syntax error at key_tb.v(5) near text "reg";  expecting an identifier ("reg" is a reserved keyword )

在用reg申明变量时结尾写成了逗号，而不是分号。