6410_clk设置

在第一个程序的基础上，APLL提升到667MHZ，MPLL设置成266MHZ，HCLKX2设置成266MHZ，HCK=133MHZ，PCLK=66MHZ。在一程序上添加了main.c里多包含了clk.h文件，main.c里增加clk_init函数，clk.h和clk_init函数如下：

/***************************************************

clk.h

***************************************************/
typedef struct
{

	unsigned long int APLL_LOCK;//APLL锁定时间，低16位
	unsigned long int MPLL_LOCK;
	unsigned long int EPLL_LOCK;
	union
	{
		unsigned long int _APLL_CON;
		struct
		{
			unsigned long int SDIV:3;
			unsigned long int reserved0:5;
			unsigned long int PDIV:6;
			unsigned long int reserved1:2;
			unsigned long int MDIV:10;
			unsigned long int reserved2:5;
			unsigned long int ENABLE;
		}APLL_CON;
	};
	union
	{
		unsigned long int _MPLL_CON;
		struct
		{
			unsigned long int SDIV:3;
			unsigned long int reserved0:5;
			unsigned long int PDIV:6;
			unsigned long int reserved1:2;
			unsigned long int MDIV:10;
			unsigned long int reserved2:5;
			unsigned long int ENABLE;
		}MPLL_CON;
	};
	union
	{
		unsigned long int _EPLL_CON0;
		struct
		{
			unsigned long int _EPLL_CON0;
		}EPLL_CON0;
	};
	union
	{
		unsigned long int _EPLL_CON1;
		struct
		{
			unsigned long int _EPLL_CON1;
		}EPLL_CON1;
	};
	union
	{
		unsigned long int _CLK_SRC;
		struct
		{
			unsigned long int APLL_SEL:1;
			unsigned long int MPLL_SEL:1;
			unsigned long int EPLL_SEL:1;
			unsigned long int reserved0:1;
			unsigned long int UHOST_SEL:2;
			unsigned long int AUDIO0_SEL:3;
			unsigned long int AUDIO1_SEL:3;
			unsigned long int UART_SEL:1;
			unsigned long int SPI0_SEL:2;
			unsigned long int SPI1_SEL:2;
			unsigned long int MMC0_SEL:2;
			unsigned long int MMC1_SEL:2;
			unsigned long int MMC2_SEL:2;
			unsigned long int IRDA_SEL:2;
			unsigned long int LCD_SEL:2;
			unsigned long int SCALER_SEL:2;
			unsigned long int DAC27_SEL:1;
			unsigned long int TV27_SEL:1;
		}CLK_SRC;
	};
	union
	{
		unsigned long int _CLK_DIV0;
		struct
		{
			unsigned long int ARM_RATIO:4;
			unsigned long int MPLL_RATIO:1;
			unsigned long int reserved0:3;
			unsigned long int HCLK_RATIO:1;
			unsigned long int	HCLKX2_RATIO:3;
			unsigned long int PCLK_RATIO:4;
			unsigned long int reserved1:2;
			unsigned long int SECUR_RATIO:2;
			unsigned long int CAM_RATIO:4;
			unsigned long int JPEG_RATIO:4;
			unsigned long int MFC_RATIO:4;
		}CLK_DIV0;
	};
	union
	{
		unsigned long int _CLK_DIV1;
		struct
		{
			unsigned long int _CLK_DIV1;
		}CLK_DIV1;
	};
	union
	{
		unsigned long int _CLK_DIV2;
		struct
		{
			unsigned long int _CLK_DIV2;
		}CLK_DIV2;
	};
	union
	{
		unsigned long int _CLK_OUT;
		struct
		{
			unsigned long int _CLK_OUT;
		}CLK_OUT;
	};
	union
	{
		unsigned long int _HCLK_GATE;
		struct
		{
			unsigned long int _HCLK_GATE;
		}HCLK_GATE;
	};
	union
	{
		unsigned long int _PCLK_GATE;
		struct
		{
			unsigned long int _PCLK_GATE;
		}PCLK_GATE;
	};
	union
	{
		unsigned long int _SCLK_GATE;
		struct
		{
			unsigned long int _SCLK_GATE;
		}SCLK_GATE;
	};
	union
	{
		unsigned long int _MEM0_CLK_GATE;
		struct
		{
			unsigned long int _MEM0_CLK_GATE;
		}MEM0_CLK_GATE;
	};
	unsigned long int reserved0[48];
	union
	{
		unsigned long int _AHB_CON0 ;
		struct
		{
			unsigned long int _AHB_CON0 ;
		}AHB_CON0;
	};
	union
	{
		unsigned long int _AHB_CON1 ;
		struct
		{
			unsigned long int _AHB_CON1 ;
		}AHB_CON1;
	};
	union
	{
		unsigned long int _AHB_CON2;
		struct
		{
			unsigned long int _AHB_CON2;
		}AHB_CON2;
	};
	union
	{
		unsigned long int _CLK_SRC2;
		struct
		{
			unsigned long int _CLK_SRC2;
		}CLK_SRC2;
	};
	union
	{
		unsigned long int _SDMA_SEL;
		struct
		{
			unsigned long int _SDMA_SEL;
		}SDMA_SEL;
	};
	unsigned long int reserved1;
	union
	{
		unsigned long int _SYS_ID;
		struct
		{
			unsigned long int _SYS_ID;
		}SYS_ID;
	};
	union
	{
		unsigned long int _SYS_OTHERS;
		struct
		{
			unsigned long int _SYS_OTHERS;
		}SYS_OTHERS;
	};
	union
	{
		unsigned long int _MEM_SYS_CFG;
		struct
		{
			unsigned long int _MEM_SYS_CFG;
		}MEM_SYS_CFG;
	};
	unsigned long int reserved2;
	union
	{
		unsigned long int _QOS_OVERRIDE1;
		struct
		{
			unsigned long int _QOS_OVERRIDE1;
		}QOS_OVERRIDE1;
	};
	union
	{
		unsigned long int _MEM_CFG_STAT;
		struct
		{
			unsigned long int _MEM_CFG_STAT;
		}MEM_CFG_STAT;
	};
	unsigned long int reserved3;
	unsigned long int reserved4[52];
	unsigned long int reserved5[16];
	unsigned long int reserved6[369];
	union
	{
		unsigned long int _PWR_CFG ;
		struct
		{
			unsigned long int _PWR_CFG ;
		}PWR_CFG ;
	};
	union
	{
		unsigned long int _EINT_MASK ;
		struct
		{
			unsigned long int _EINT_MASK ;
		}EINT_MASK ;
	};
	unsigned long int reserved7;
	union
	{
		unsigned long int _NORMAL_CFG;
		struct
		{
			unsigned long int _NORMAL_CFG;
		}NORMAL_CFG ;
	};
	union
	{
		unsigned long int _STOP_CFG;
		struct
		{
			unsigned long int _STOP_CFG;
		}STOP_CFG ;
	};
	union
	{
		unsigned long int _SLEEP_CFG;
		struct
		{
			unsigned long int _SLEEP_CFG;
		}SLEEP_CFG ;
	};
	union
	{
		unsigned long int _STOP_MEM_CFG;
		struct
		{
			unsigned long int _STOP_MEM_CFG;
		}STOP_MEM_CFG ;
	};
	union
	{
		unsigned long int _OSC_FREQ;
		struct
		{
			unsigned long int _OSC_FREQ;
		}OSC_FREQ ;
	};
	union
	{
		unsigned long int _OSC_STABLE;
		struct
		{
			unsigned long int _OSC_STABLE;
		}OSC_STABLE ;
	};
	union
	{
		unsigned long int _PWR_STABLE;
		struct
		{
			unsigned long int _PWR_STABLE;
		}PWR_STABLE ;
	};
	unsigned long int reserved8;
	union
	{
		unsigned long int _MTC_STABLE;
		struct
		{
			unsigned long int _MTC_STABLE;
		}MTC_STABLE;
	};
	union
	{
		unsigned long int _MISC_CON;
		struct
		{
			unsigned long int _MISC_CON;
		}MISC_CON;
	};
	unsigned long int served9[50];
	union
	{
		unsigned long int _OTHERS;
		struct
		{
			unsigned long int CP15DISABLE:1;
			unsigned long int reserved0:1;
			unsigned long int reserved1:1;
			unsigned long int reserved2:3;//此处不要改变
			unsigned long int SYNCMUXSEL:1;
			unsigned long int SYNCMODE:1;
			unsigned long int SYNCACK:4;
			unsigned long int CLEAR_BATF_INT:1;
			unsigned long int CLEAR_DBGACK:1;
			unsigned long int reserved3:2;
			unsigned long int USB_SIG_MASK:1;
			unsigned long int reserved4:6;
			unsigned long int STABLE_COUNTER_TYPE:1;
			unsigned long int reserved5:8;
		}OTHERS;
	};
	union
	{
		unsigned long int _RST_STAT;
		struct
		{
			unsigned long int _RST_STAT;
		}RST_STAT;
	};
	union
	{
		unsigned long int _WAKEUP_STAT;
		struct
		{
			unsigned long int _WAKEUP_STAT;
		}WAKEUP_STAT;
	};
	union
	{
		unsigned long int _BLK_PWR_STAT;
		struct
		{
			unsigned long int _BLK_PWR_STAT;
		}BLK_PWR_STAT;
	};
	union
	{
		unsigned long int _INFORM0;
		struct
		{
			unsigned long int _INFORM0;
		}INFORM0;
	};
	union
	{
		unsigned long int _INFORM1;
		struct
		{
			unsigned long int _INFORM1;
		}INFORM1;
	};
	union
	{
		unsigned long int _INFORM2;
		struct
		{
			unsigned long int _INFORM2;
		}INFORM2;
	};
	union
	{
		unsigned long int _INFORM3;
		struct
		{
			unsigned long int _INFORM3;
		}INFORM3;
	};
	
}clock;

/**************************************************************************

 

void clk_init(void)

 

**************************************************************************/

void clk_init(void)
{
	(CLK_BASE->CLK_SRC).APLL_SEL=0;//12MHZ晶振
	(CLK_BASE->CLK_SRC).MPLL_SEL=0;
	
	CLK_BASE->APLL_LOCK=0xffff;
	CLK_BASE->MPLL_LOCK=0xffff;
//	CLK_BASE->EPLL_LOCK=0xffff;
	CLK_BASE->_APLL_CON=1<<31 | 333<<16 | 3<<8 | 1<<0;//APLL 667MHZ
	CLK_BASE->_MPLL_CON=1<<31 | 266<<16 | 3<<8 | 2<<0;//MPLL 266MHZ
	
	(CLK_BASE->CLK_DIV0).ARM_RATIO=0;//armclk667mhz
	(CLK_BASE->CLK_DIV0).HCLKX2_RATIO=0;//hclkx2266mhz
	(CLK_BASE->CLK_DIV0).HCLK_RATIO=1;//hclk133mhz
	(CLK_BASE->CLK_DIV0).PCLK_RATIO=3;//pclk66mhz
	
	(CLK_BASE->OTHERS).SYNCMUXSEL=0;//进入异步模式
	(CLK_BASE->OTHERS).SYNCMODE=0;
	while(0!=0!=CLK_BASE->OTHERS.SYNCACK);//等待进入异步模式
	
	(CLK_BASE->CLK_SRC).APLL_SEL=1;
	(CLK_BASE->CLK_SRC).MPLL_SEL=1;
	
	
	
}