叶 2014年10月18日~2014年10月24日
本周已完成任务:测频、测周期
本周未完成任务:测幅值
下周计划:完善AD采集后测幅值
关键技术点说明:
上图为所设计的测频原理图,图中CLOCK即为时钟频率50MHz,将50MHz进行分频为10KHz,程序段如下:
module fregate
(
clk, gateout
);
input clk;
output gateout;
reg gateout, gatebuf;
reg [22:0] cnt;
always @(posedge clk)
begin
if (cnt == 23'd5000)
begin
gatebuf <= ~gatebuf;
gateout <= gatebuf;
cnt <= 23'd0;
end
else
cnt <= cnt + 23'd1;
end
endmodule
10KHz作为标准频率信号,再将此时钟进行计数1000次,得到预设的100ms闸门信号,通过D触发器,触发器由被测信号上升沿触发,高电平作为计数器的使能信号,两个计数器分别在闸门范围内进行计数。计数器的程序段如下:
module cnt
(
clk, gate, cntout
);
input clk;
input gate;
output [19:0] cntout ;
reg [19:0] cnt, cntout;
reg gatebuf;
always @(posedge clk)
gatebuf <= gate;
always @(posedge clk)
begin
if((gate == 1'b1) && (gatebuf == 1'b0))
begin
cnt <= 20'd1;
end
else if((gate == 1'b0) && (gatebuf == 1'b1))
begin
cntout <= cnt;
end
else if(gatebuf == 1'b1)
begin
cnt <= cnt + 20'd1;
end
end
endmodule
计数器结果再进行计算,计算程序段如下:
module frediv
(
clk, datat,datas, freout
);
input clk;
input [19:0] datas;
input [19:0] datat;
output [19:0] freout;
reg [19:0] datam,freout, databbuf;
reg [19:0] cbuf;
reg [19:0] temp;
reg finish, cntflag;
always @(posedge clk)
begin
if((finish == 1'b0) && (datas != 20'd0) && (datat != 20'd0))
begin
datam <= 20'd10000 * datat;
temp <= datas;
cbuf <= 20'd1;
databbuf <= datas;
cntflag <= 1'b1;
finish <= 1'b1;
end
else if ((datam > temp) && (cntflag == 1'b1) )
begin
temp <= temp + databbuf;
cbuf <= cbuf + 20'd1;
end
else
begin
freout <= cbuf;
finish <= 1'b0;
cntflag <= 1'b0;
end
end
endmodule
因为标准信号频率设为10KHz,程序段中两者结果比较,得出被测信号的频率结果。再接入单片机进行数据处理,送显。