面向小白：Nand2Tetris（计算机系统要素）Hack计算机实现过程1 - 布尔逻辑

1. 项目概况

1.1 课程简介

从大佬的cs自学指南里偶然发现Nand2Tetris这门神奇的课程，居然是无门槛的计算机课程，居然能从 01 开始让你亲手造出一台计算机，对于新手小白来说他不香吗？？不管那么多了，果断开始学习，我也要拥有自己的计算机！(狂敲键盘)(兴奋地尖叫)(开心地打滚)

1.2 Project1需求清单

仅使用原始门Nand（可以使用基于Nand构件的复合门）构建下方所有逻辑门，格式参考Nand门芯片程序。

芯片名	对应逻辑门	功能
Not	非门/反相器	将1反相为0输出，或将0反相为1输出
And	与门	只有当输入都为1时，输出才是1，否则均输出0
Or	或门	只要输入变量中有1，就输出1，否则输出0
Xor	异或门	当两个输入值相反时，输出1，否则输出0
Mux	选择器	根据输入选择位的值，决定输出哪一个输入数据位的值
DMux	分配器	根据输入选择位的值，决定将输入数据位的值分配给哪一个输出通道
Not16	16位非门	对16位输入总线上的每一位取反，然后输出
And16	16位与门	对两个16位输入总线上的每一对输入变量进行And操作，然后输出
Or16	16位或门	对两个16位输入总线上对应的每一对输入变量进行Or操作，然后输出
Mux16	16位选择器	根据输入选择位的值，决定输出哪一个输入变量的值（每个输入变量都是16位）
Or8Way	8通道8位或门	当8位输入变量中任意一位或一位以上为1，输出为1，否则输出为0
Mux4Way16	4通道16位选择器	根据 $k={\log }_{2}4=2$ 个输入选择位的值，将4个16位输入变量中选择一个并从其单一的16位输出总线上输出
Mux8Way16	8通道16位选择器	根据 $k={\log }_{2}8=3$ 个输入选择位的值，将8个16位输入变量中选择一个并从其单一的16位输出总线上输出
DMux4Way	4通道1位分配器	根据 $k={\log }_{2}4=2$ 个输入选择位的值，从4个可能的输出通道中选择一个，用于输出1位的输入变量
DMux8Way	4通道1位分配器	根据 $k={\log }_{2}8=2$ 个输入选择位的值，从8个可能的输出通道中选择一个，用于输出1位的输入变量

附 格式参考：
Project1使用API描述芯片，则用于实现Nand门的芯片描述如下：

信息项	描述
芯片名	Nand
输入	a, b
输出	out
功能	If a=b=1 then out=0 else out=1
说明	此门是最基本的单元，不需要实现

作为本项目中最基本的单元，Nand已经用HDL实现（相应文件在 .\nand2tetris\tools\builtInChips\Nand.hdl）

/**
 * Nand gate: out = a Nand b.
 */

CHIP Nand {

    IN  a, b;
    OUT out;

    BUILTIN Nand;
}

2. 软件安装和环境配置

设备：个人计算机一台，本人使用的是华硕K550J。实际上对配置要求很低，一般计算机都可以。
软件：到nand2tetris课程官网下载Nand2tetris Software Suite（如图1），并安装JRE运行环境（因为课程使用的软件是用Java开发的）。JRE推荐在Oracle官网下载（如图2）。

3. .hdl程序编写、载入和测试方法（以Not为例）

以Not门为例，介绍HDL程序编写、载入和测试方法。

3.1 .hdl程序编写

用于实现Not门的芯片描述如下：

信息项	描述
芯片名	Not
输入	in
输出	out
功能	If in = 0 then out = 1, else out = 0

分析：$\text{Not}(in)=in\text{ Nand }in$

用HDL实现Not（直接在已有文件中修改，位置为 .\nand2tetris\projects\01\Not.hdl）：

// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/01/Not.hdl
 /**
 * Not gate:
 * out = ((in == 0), 1, 0)
 */
CHIP Not {
    IN in;
    OUT out;
    
    PARTS:
    Nand (a = in, b = in, out = out);
}

3.2 .hdl程序载入

找到nand2tetris安装目录，双击打开.\nand2tetris\tools文件夹中的HardwareSimulator.bat，如图3。
如图4，软件界面打开后，单击左上角的芯片形状图标，选择刚编辑保存好的.hdl文件，点击Load Chip载入。图5为载入成功后的界面，可以看到芯片名称、管脚和HDL程序代码。

3.3 程序测试

如图6，点击脚本图标，选择与.hdl文件相匹配的测试脚本，点击Load Script载入。图7为测试脚本载入后的界面，脚本内容会显示在右侧。


如图8，如果看不到下方提示栏，鼠标点击底部边缘将其拉出。提示信息很重要，用于确认程序是否正确执行。点击左上运行按钮，执行测试。如果程序正确，会在下方信息栏提示Comparison ended successfully，如图9所示。

4. 除Not外的其他芯片实现过程

4.1 And

用于实现And门的芯片描述如下：

信息项	描述
芯片名	And
输入	a, b
输出	out
功能	If ((a == 1) and (b == 1)) then out = 1, else out = 0

分析：$a\text{ And }b=(a\text{ Nand }b)\text{ Nand }(a\text{ Nand }b)$

用HDL实现And（直接在已有文件中修改，位置为 .\nand2tetris\projects\01\And.hdl）：

// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/01/And.hdl
/**
 * And gate:
 * out = (((a == 1) && (b == 1))), 1, 0) 
 */
CHIP And {
    IN a, b;
    OUT out;
    
    PARTS:
    Nand (a = a, b = b, out = w1);
    Nand (a = w1, b = w1, out = out);
}

4.2 Or

用于实现Or门的芯片描述如下：

信息项	描述
芯片名	Or
输入	a, b
输出	out
功能	If a = b = 0 then out = 0, else out = 1

分析：$a\text{ Or }b=(\text{Not }(a))\text{ Nand }(\text{Not }(b))$

用HDL实现Or（直接在已有文件中修改，位置为 .\nand2tetris\projects\01\Or.hdl）：

// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/01/Or.hdl
/**
 * Or gate:
 * out = (((a == 1) || (b == 1))), 1, 0) 
 */
CHIP Or {
    IN a, b;
    OUT out;

    PARTS:
    Not (in = a, out = w1);
    Not (in = b, out = w2);
    Nand (a = w1, b = w2, out = out);
}

4.3 Xor

用于实现Xor门的芯片描述如下：

信息项	描述
芯片名	Xor
输入	a, b
输出	out
功能	If a = /b then out = 1, else out = 0

分析：$a\text{ Xor }b=(\text{Not }(a)\text{ And }b)\text{ Or }(a\text{ And }\text{Not }(b))$

用HDL实现Xor（直接在已有文件中修改，位置为 .\nand2tetris\projects\01\Xor.hdl）：

// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/01/Xor.hdl
/**
 * Exclusive-or gate:
 * out = (((a == 0) & (b = 1)) | ((a == 1) & (b = 0)), 1, 0)
 */
CHIP Xor {
    IN a, b;
    OUT out;

    PARTS:
    Not (in = a, out = nota);
    Not (in = b, out = notb);
    And (a = nota, b = b, out = w1);
    And (a = a, b = notb, out = w2);
    Or (a = w1, b = w2, out = out);
}

4.4 Multiplexor

用于实现Multiplexor门的芯片描述如下：

信息项	描述
芯片名	Mux
输入	a, b, sel
输出	out
功能	If sel = 0 then out = a, else out = b

分析：$\text{Mux}(a,b,sel)=(a\text{ And }\text{Not}(sel))\text{ Or }(b\text{ And }sel)$

用HDL实现Mux（直接在已有文件中修改，位置为 .\nand2tetris\projects\01\Mux.hdl）：

// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/01/Mux.hdl
/** 
 * Multiplexor:
 * out = ((sel == 0), a, b)
 */
CHIP Mux {
    IN a, b, sel;
    OUT out;

    PARTS:
    Not (in = sel, out = notsel);
    And (a = a, b = notsel, out = w1);
    And (a = b, b = sel, out = w2);
    Or (a = w1, b = w2, out = out);
}

4.5 Demultiplexor

用于实现Demultiplexor门的芯片描述如下：

信息项	描述
芯片名	DMux
输入	in, sel
输出	a, b
功能	If sel = 0 then (a = in, b = 0), else (a = 0, b = in)

分析：$a=\text{Not}(sel)\text{ And }in\text{, }b=sel\text{ And }in$

用HDL实现DMux（直接在已有文件中修改，位置为 .\nand2tetris\projects\01\DMux.hdl）：

// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/01/DMux.hdl
/**
 * Demultiplexor:
 * [a, b] = ((sel == 0), [in, 0], [0, in])
 */
CHIP DMux {
    IN in, sel;
    OUT a, b;

    PARTS:
    Not (in = sel, out = notsel);
    And (a = in, b = notsel, out = a);
    And (a = in, b = sel, out = b);
}

4.6 16位Not

用于实现16位Not门的芯片描述如下：

信息项	描述
芯片名	Not16
输入	in[16]
输出	out[16]
功能	For i = 0…15 out[i] = Not(in[i])

分析：$\text{out}[i]=\text{Not}(in[i])$

用HDL实现Not16（直接在已有文件中修改，位置为 .\nand2tetris\projects\01\Not16.hdl）：

// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/01/Not16.hdl
/**
 * 16-bit Not gate:
 * out[i] = ((in[i] == 0), 1, 0) for i = 0..15 
 */
CHIP Not16 {
    IN in[16];
    OUT out[16];

    PARTS:
    Not (in = in[0], out = out[0]);
    Not (in = in[1], out = out[1]);
    Not (in = in[2], out = out[2]);
    Not (in = in[3], out = out[3]);
    Not (in = in[4], out = out[4]);
    Not (in = in[5], out = out[5]);
    Not (in = in[6], out = out[6]);
    Not (in = in[7], out = out[7]);
    Not (in = in[8], out = out[8]);
    Not (in = in[9], out = out[9]);
    Not (in = in[10], out = out[10]);
    Not (in = in[11], out = out[11]);
    Not (in = in[12], out = out[12]);
    Not (in = in[13], out = out[13]);
    Not (in = in[14], out = out[14]);
    Not (in = in[15], out = out[15]);
}

4.7 16位And

用于实现16位And门的芯片描述如下：

信息项	描述
芯片名	And16
输入	in[16]
输出	out[16]
功能	For i = 0…15 out[i] = And(a[i], b[i])

分析：$\text{out}[i]=a[i]\text{ And }b[i]$

用HDL实现And16（直接在已有文件中修改，位置为 .\nand2tetris\projects\01\And16.hdl）：

// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/01/And16.hdl
/**
 * 16-bit bitwise And gate:
 * out[i] = And(a[i],b[i]) for i = 0..15 
 */
CHIP And16 {
    IN a[16], b[16];
    OUT out[16];

    PARTS:
    And (a = a[0], b = b[0], out = out[0]);
    And (a = a[1], b = b[1], out = out[1]);
    And (a = a[2], b = b[2], out = out[2]);
    And (a = a[3], b = b[3], out = out[3]);
    And (a = a[4], b = b[4], out = out[4]);
    And (a = a[5], b = b[5], out = out[5]);
    And (a = a[6], b = b[6], out = out[6]);
    And (a = a[7], b = b[7], out = out[7]);
    And (a = a[8], b = b[8], out = out[8]);
    And (a = a[9], b = b[9], out = out[9]);
    And (a = a[10], b = b[10], out = out[10]);
    And (a = a[11], b = b[11], out = out[11]);
    And (a = a[12], b = b[12], out = out[12]);
    And (a = a[13], b = b[13], out = out[13]);
    And (a = a[14], b = b[14], out = out[14]);
    And (a = a[15], b = b[15], out = out[15]);
}

4.8 16位Or

用于实现16位Or门的芯片描述如下：

信息项	描述
芯片名	Or16
输入	in[16]
输出	out[16]
功能	For i = 0…15 out[i] = Or(a[i], b[i])

分析：$\text{out}[i]=a[i]\text{ Or }b[i]$

用HDL实现Or16（直接在已有文件中修改，位置为 .\nand2tetris\projects\01\Or16.hdl）：

// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/01/Or16.hdl
/**
 * 16-bit bitwise Or gate:
 * out[i] = (a[i] Or b[i]) for i = 0..15 
 */
CHIP Or16 {
    IN a[16], b[16];
    OUT out[16];

    PARTS:
    Or (a = a[0], b = b[0], out = out[0]);
    Or (a = a[1], b = b[1], out = out[1]);
    Or (a = a[2], b = b[2], out = out[2]);
    Or (a = a[3], b = b[3], out = out[3]);
    Or (a = a[4], b = b[4], out = out[4]);
    Or (a = a[5], b = b[5], out = out[5]);
    Or (a = a[6], b = b[6], out = out[6]);
    Or (a = a[7], b = b[7], out = out[7]);
    Or (a = a[8], b = b[8], out = out[8]);
    Or (a = a[9], b = b[9], out = out[9]);
    Or (a = a[10], b = b[10], out = out[10]);
    Or (a = a[11], b = b[11], out = out[11]);
    Or (a = a[12], b = b[12], out = out[12]);
    Or (a = a[13], b = b[13], out = out[13]);
    Or (a = a[14], b = b[14], out = out[14]);
    Or (a = a[15], b = b[15], out = out[15]);
}

4.9 16位Multiplexor

用于实现16位Multiplexor门的芯片描述如下：

信息项	描述
芯片名	Mux16
输入	a[16], b[16], sel
输出	out[16]
功能	If sel = 0 then for i = 0…15 out[i] = a[i], else for i = 0…15 out[i] = b[i]

分析：$\text{out}[i]=(a[i]\text{ And }\text{Not}(sel))\text{ Or }(b[i]\text{ And }sel)$

用HDL实现Mux16（直接在已有文件中修改，位置为 .\nand2tetris\projects\01\Mux16.hdl）：

// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/01/Mux16.hdl
/**
 * 16-bit multiplexor: 
 * out[i] = ((sel == 0), a[i], b[i]) for i = 0..15
 */
CHIP Mux16 {
    IN a[16], b[16], sel;
    OUT out[16];

    PARTS:
    Mux (a = a[0], b = b[0], sel = sel, out = out[0]);
    Mux (a = a[1], b = b[1], sel = sel, out = out[1]);
    Mux (a = a[2], b = b[2], sel = sel, out = out[2]);
    Mux (a = a[3], b = b[3], sel = sel, out = out[3]);
    Mux (a = a[4], b = b[4], sel = sel, out = out[4]);
    Mux (a = a[5], b = b[5], sel = sel, out = out[5]);
    Mux (a = a[6], b = b[6], sel = sel, out = out[6]);
    Mux (a = a[7], b = b[7], sel = sel, out = out[7]);
    Mux (a = a[8], b = b[8], sel = sel, out = out[8]);
    Mux (a = a[9], b = b[9], sel = sel, out = out[9]);
    Mux (a = a[10], b = b[10], sel = sel, out = out[10]);
    Mux (a = a[11], b = b[11], sel = sel, out = out[11]);
    Mux (a = a[12], b = b[12], sel = sel, out = out[12]);
    Mux (a = a[13], b = b[13], sel = sel, out = out[13]);
    Mux (a = a[14], b = b[14], sel = sel, out = out[14]);
    Mux (a = a[15], b = b[15], sel = sel, out = out[15]);
}

4.10 8通道8位Or

用于实现8通道8位Or门的芯片描述如下：

信息项	描述
芯片名	Or8Way
输入	in[8]
输出	out
功能	out = Or(in[0], in[1], …, in[7])

分析：$\text{out}=\text{in}[0]\text{ Or }\text{in}[1]\text{ Or }\text{...}\text{in}[7]$

用HDL实现Or8Way（直接在已有文件中修改，位置为 .\nand2tetris\projects\01\Or8Way.hdl）：

// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/01/Or8Way.hdl
/**
 * 8-way Or gate: 
 * out = in[0] Or in[1] Or ... Or in[7]
 */
CHIP Or8Way {
    IN in[8];
    OUT out;

    PARTS:
    Or (a = in[0], b = in[1], out = w1);
    Or (a = w1, b = in[2], out = w2);
    Or (a = w2, b = in[3], out = w3);
    Or (a = w3, b = in[4], out = w4);
    Or (a = w4, b = in[5], out = w5);
    Or (a = w5, b = in[6], out = w6);
    Or (a = w6, b = in[7], out = out);
}

4.11 4通道16位Multiplexor

用于实现4通道16位Multiplexor门的芯片描述如下：

信息项	描述
芯片名	Mux4Way16
输入	a[16], b[16], c[16], d[16], sel[2]
输出	out[16]
功能	If sel = 00 then out = a, else if sel = 01 then out = b, else if sel = 10 then out = c, else if sel = 11 then out = d
说明	上述赋值操作都是16-位操作。比如：“out=a"指"for i=0…15 out[i]=a[i]”

分析：$\text{out}=(a\text{ And }(\text{Not}(sel[0])\text{ And }\text{Not}(sel[1])))\text{ Or }(b\text{ And }(\text{Not}(sel[0])\text{ And }sel[1]))\text{ Or }(c\text{ And }(sel[0]\text{ And }\text{Not}(sel[1]))\text{ Or }(d\text{ And }(sel[0]\text{ And }sel[1])$

用HDL实现Mux4Way16（直接在已有文件中修改，位置为 .\nand2tetris\projects\01\Mux4Way16.hdl），要注意，在.hdl中，如果sel = 01，则sel[1] = 0，sel[0] = 1，也就是倒序的。

// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/01/Mux4Way16.hdl
/**
 * 4-way 16-bit multiplexor:
 * out = a if sel == 00
 *       b if sel == 01
 *       c if sel == 10
 *       d if sel == 11
 */
CHIP Mux4Way16 {
    IN a[16], b[16], c[16], d[16], sel[2];
    OUT out[16];
    
    PARTS:
    Mux16 (a = a, b = b, sel = sel[0], out = aMuxb);
    Mux16 (a = c, b = d, sel = sel[0], out = cMuxd);
    Mux16 (a = aMuxb, b = cMuxd, sel = sel[1], out = out);
}

4.12 8通道16位Multiplexor

用于实现8通道16位Multiplexor门的芯片描述如下：

信息项	描述
芯片名	Mux8Way16
输入	a[16], b[16], c[16], d[16], e[16], f[16], g[16], h[16], sel[3]
输出	out[16]
功能	If sel = 000 then out = a, else if sel = 001 then out = b, else if sel = 010 then out = c, else if sel = 011 then out = d, else if sel = 100 then out = e, else if sel = 101 then out = f, else if sel = 110 then out = g, else if sel = 111 then out = h
说明	上述赋值操作都是16-位操作。比如：“out=a"指"for i=0…15 out[i]=a[i]”

分析：$\text{out}=(a\text{ And }(\text{Not}(sel[0])\text{ And }\text{Not}(sel[1])\text{ And }\text{Not}(sel[2])))\text{ Or }(b\text{ And }(\text{Not}(sel[0])\text{ And }\text{Not}(sel[1])\text{ And }sel[2]))\text{...Or }(h\text{ And }(sel[0]\text{ And }sel[1]\text{ And }sel[2]))$

用HDL实现Mux4Way16（直接在已有文件中修改，位置为 .\nand2tetris\projects\01\Mux4Way16.hdl）：

// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/01/Mux8Way16.hdl
/**
 * 8-way 16-bit multiplexor:
 * out = a if sel == 000
 *       b if sel == 001
 *       ...
 *       h if sel == 111
 */
CHIP Mux8Way16 {
    IN a[16], b[16], c[16], d[16],
       e[16], f[16], g[16], h[16],
       sel[3];
    OUT out[16];

    PARTS:
    Mux4Way16 (a = a, b = b, c = c, d = d, sel = sel[0..1], out = Muxabcd);
    Mux4Way16 (a = e, b = f, c = g, d = h, sel = sel[0..1], out = Muxefgh);
    Mux16 (a = Muxabcd, b = Muxefgh, sel = sel[2], out = out);
}

4.13 4通道1位Demultiplexor

用于实现4通道1位Demultiplexor门的芯片描述如下：

信息项	描述
芯片名	DMux4Way
输入	in, sel[2]
输出	a, b, c, d
功能	If sel = 00 then {a = in, b = c = d = 0}, else if sel = 01 then {b = in, a = c = d = 0}, else if sel = 10 then {c = in, a = b = d = 0}, else if sel = 11 then {d = in, a = b = c = 0}

用HDL实现DMux4Way（直接在已有文件中修改，位置为 .\nand2tetris\projects\01\DMux4Way.hdl）：

// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/01/DMux4Way.hdl
/**
 * 4-way demultiplexor:
 * [a, b, c, d] = [in, 0, 0, 0] if sel == 00
 *                [0, in, 0, 0] if sel == 01
 *                [0, 0, in, 0] if sel == 10
 *                [0, 0, 0, in] if sel == 11
 */
CHIP DMux4Way {
    IN in, sel[2];
    OUT a, b, c, d;

    PARTS:
    DMux (in = in, sel = sel[1], a = w1, b = w2);
    DMux (in = w1, sel = sel[0], a = a, b = b);
    DMux (in = w2, sel = sel[0], a = c, b = d);
}

4.14 8通道1位Demultiplexor

用于实现8通道1位Demultiplexor门的芯片描述如下：

信息项	描述
芯片名	DMux8Way
输入	in, sel[3]
输出	a, b, c, d, e, f, g, h
功能	If sel = 000 then {a = in, b = c = d = e = f = g = h = 0}, else if sel = 001 then {b = in, a = c = d = e = f = g = h = 0},…, else if sel = 111 then {h = in, a = b = c = d = e = f = g = 0}

用HDL实现DMux8Way（直接在已有文件中修改，位置为 .\nand2tetris\projects\01\DMux8Way.hdl）：

// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/01/DMux8Way.hdl
/**
 * 8-way demultiplexor:
 * [a, b, c, d, e, f, g, h] = [in, 0, 0, 0, 0, 0, 0, 0] if sel == 000
 *                            [0, in, 0, 0, 0, 0, 0, 0] if sel == 001
 *                            ...
 *                            [0, 0, 0, 0, 0, 0, 0, in] if sel == 111
 */
CHIP DMux8Way {
    IN in, sel[3];
    OUT a, b, c, d, e, f, g, h;

    PARTS:
    DMux4Way (in = in, sel = sel[1..2], a = w1, b = w2, c = w3, d = w4);
    DMux (in = w1, sel = sel[3], a = a, b = b);
    DMux (in = w2, sel = sel[3], a = c, b = d);
    DMux (in = w3, sel = sel[3], a = e, b = f);
    DMux (in = w4, sel = sel[3], a = g, b = h);
}

5. 总结

5.1 遇到的问题和解决办法

（1）一开始看官方的课程，觉得效率低下，有点受打击。
仔细思考一下，发现个人听课效率一般都较低，远不如自己看书学习。所以找出课程作者的配套书籍《计算机系统要素 从零开始构建现代计算机》，自己看书自学，效果好多啦。
（2）第一次使用CSDN，文章编辑过程中网页总是卡住。
搜索了一下找到一个不错的办法：使用谷歌无痕模式+手机热点，完美解决问题。参考文章
（3）刚开始编写多通道逻辑门芯片HDL代码时，总是测试不通过。
怀疑是sel数组没用对，搜索了一下果然，在这里所用的HDL语言中，sel是倒序，即sel = 01时，sel[0]表示右起第一个数字1，而sel[1]表示右起第二个数字0。如果用反了自然会出错。参考文章
（4）有时刚编写好的程序文件，点击载入后并没有显示在界面中。
载入几次都还是失败，怀疑是程序本身写错了。检查了一下发现粗心大意，把逗号,写成了点.。属于是小白容易犯的低级错误，应该尽量避免。
（5）个别程序怎么也写不对，或者根本不会写。
小白上路就是磕磕绊绊，好在有前人的文章可以参考，真是帮了大忙。参考文章

5.2 心得体会

非科班纯小白，持续投入四天也能完成这一优秀项目的第一部分！虽然过程有点煎熬，但是非常值得，有了继续的信心！