/*---------深度16,位宽8bit同步fifo-----------*/
module Syn_fifo (
input clk,
input rst_n,
input wr_en,
input rd_en,
input [7:0] din, //fifo 位宽
output reg [7:0] dout,
output full,empty
);
reg [3:0] wr_ptr;
reg [3:0] rd_ptr;
reg [3:0] cnt;
reg [7:0] mem[0:15];
assign full = (cnt == 4'd15);
assign empty = (cnt == 4'd0);
/*---------cnt;else 中含同时读写--------*/
always@(posedge clk or negedge rst_n)
if (!rst_n)
cnt <= 4'd0;
else if (!full && wr_en)
cnt <= cnt + 4'd1;
else if (!empty && rd_en)
cnt <= cnt - 4'd1;
else
cnt <= cnt;
/*-------------读数据----------------*/
always@(posedge clk or negedge rst_n)
if (!rst_n)
dout <= 8'd0;
else if (rd_en && !empty)
dout <= mem[rd_ptr]
/*-------------写数据--------------*/
always@(posedge clk)
if (wr_en && !full)
mem[wr_ptr] <=din;
/*-----------更新读写指针-------------*/
always@(posedge clk or negedge rst_n)
if (!rst_n)
wr_ptr <= 4'b0;
else if(!full && wr_en)
wr_ptr <=wr_ptr + 4'd1;
else
wr_ptr <=wr_ptr;
always@(posedge clk or negedge rst_n)
if (!rst_n)
rd_ptr <= 4'd0;
else if(!empty && rd_en)
rd_ptr <=rd_ptr - 4'd1;
else
rd_ptr <=rd_ptr;
endmodule
同步 FIFO
最新推荐文章于 2024-07-24 16:49:06 发布