1. Principal Application Engineer-Physical Design
Position Description:
To provide key technical support in digital IC design implementation, product demonstration, and sales presentations.
To demonstrate strong ability and to be hands-on in RTL-to-GDSII design methodology, for challenging low power designs, for 200MHz to several GHz big chips.
Have real design experience including conformal check, logic synthesis, P&R, CTS, SSTA, MMMC to close timing, power and die area.
Assist in technical evaluation, assessment and delivery of concurrent ASIC/SoC designs.
To play a leading role among other team members, while receive little instruction on routine and general assignments.
Position Requirements:
A bachelor's degree is essential and 7+ years’ experience in IC design, electronic engineering or computer science applications.
Ability to understand and articulate technical issues, (and knowledge of) design products and their applications.
Requires working knowledge of one or more programming languages, and effective communication and soft skills.
An MS degree and/or working experience in multi-nation IC design house is a plus.
2. Principal/Lead Application Engineer - Tensilica IP (SZ)
Position Description:
As the member of the APAC Tensilica IP Field Applications Engineering (FAE) Team, you will participate in driving technical and business campaign success with industry leading semiconductor and system companies.
Understand Cadence’s end customer’s IP needs and provide front line technical support in Pre-Sales and Post-Sales process.
Champion the customer needs and work with Sales Team, R&D and Product Marketing to develop competitive and creative technical solutions to win campaigns
Be a key contributor driving product roadmap direction for our next generation products
Position Requirements:
BS degree in Electrical Engineering/Computer Science or related field
At least 5+ years of SoC and/or embedded software or DSP algorithm design experience
Have strong customer facing skills to be able to establish technical & management credibility with the key technical decision makers
Have experience and/or knowledge of one or more of Digital Audio, DSP, imaging or computer vision technologies
Previous experience with DSP processor core (Tensilica Xtensa is preferred) or derivatives is highly desirable
Experience with DSP & CPU architectures desirable – including architectural, software or HW/Debug related
Experience of embedded software process for DSP development is beneficial, particularly for embedded DSP core architectures
3. Lead Application Engineer- Frontend Verification
Position Description:
Work closely with the Sales team to identify and scope opportunities for Cadence Emulation and Acceleration products.
Plan, execute and manage key technical evaluations and benchmark with existing and potential customers.
Train, ramp-up and accompany customer project.
Conduct basic and advanced trainings, presentations and demos as necessary.
Providing technical expertise to address clients’ queries, which need expert involvement.
Aligned closely with corporate engineering and sales/marketing team on customer requirement for product direction/improvement.
Position Requirements:
4~6 years’ experience in the following areas:
HW verification with knowledge of System Verilog/VHDL and HDL simulators
FPGA prototyping project experience is a must
Experience with hardware emulator or accelerator is a big advantage
Advanced Verification Methodology like UVM is a plus
Knowledge of Unix and Linux is highly desired
Strong verbal and written communication skills in English
Strong teamwork skills with good human relationship
4. Principal Application Engineer - Frontend Verification
Position Description:
Work closely with the Sales team to identify and scope opportunities for Cadence SoC Verification solution, simulation Emulation and Acceleration products.
Plan, execute and manage key technical evaluations and benchmark with existing and potential customers.
Train, ramp-up and accompany customer project.
Conduct basic and advanced trainings, presentations and demos as necessary.
Providing technical expertise to address clients’ queries, which need expert involvement.
Aligned closely with corporate engineering and sales/marketing team on customer requirement for product direction/improvement.
Position Requirements:
4~10 years’ experience in the following areas:
Design experience in Verilog/VHDL for IP or SoC chip level.
HW verification with knowledge of System Verilog/VHDL and HDL simulators
FPGA prototyping project experience
Experience with hardware emulator or accelerator is a big advantage
Advanced Verification Methodology like UVM is a plus
Knowledge of Unix and Linux is highly desired
Strong verbal and written communication skills in English
Strong teamwork skills with good human relationship
5. Principal/Lead Application Engineer- Frontend Design
Position Description:
Providing direct technical support to customers in presale stage to persuade customers to adopt Cadence Design IP solutions for their applications
Interface with customer architects and IP business unit to enable evaluation of application specific IP performance and features per customer’s SoC requirements.
Working with the sales team to manage the IP activities in the region to achieve a high customer satisfaction rate and for building strong customer relationships
Providing customer feedback on new/existing requirements for Design IP usage from customers to the R&D business unit
Providing direct technical customer support and assistance to enable customers to successfully integrate/use Design IP in their SoC
Writing application notes and review protocol specifications for Design IP
Position Requirements:
Experience in SoC design
Good understanding of SoC architecture
Experience with DDR subsystem hardware or firmware testing or debugging
Good understanding DDR protocols and knowledgeable for DDR IP
Good written and verbal communication skills and problem solving skills are required
Ability to conduct technical meetings, presentations, seminars and training to customers and to the sales team
Travel within AP region may be required.
Good understanding of the semiconductor IP marketplace and ecosystem is a plus
，数字后端，数字前端，模拟layout，软件工程师，机器学习等相关人才
marco3260@163.com
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