IIC复习
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具体时序图参考
https://zhuanlan.zhihu.com/p/556505577
clock Stretch
现象:SCL半高
原因:主机不支持 从机的clock stretch功能
现象:SCL上的毛刺引发SDA误动作
原因:不考虑clock stretch时,IIC的逻辑是在SCL高电平时检测SDA的电平;考虑clock stretch时,主机检测SCL是否是高电平,此时易受毛刺干扰
repeated start
应用场景:
https://blog.csdn.net/weixin_44124323/article/details/118824527
可结合CRC校验
https://blog.csdn.net/danchaofan1982/article/details/97793240
实战总结
https://blog.csdn.net/Holden_Liu/article/details/109174743
I2C timing specifications
- Rise (tr) and Fall (tf) Times
- Setup and Hold Times
- Start Condition (Setup and Hold Time)
- Stop Condition (Setup)
- Data (Setup): 待采样数据变稳定 SCL上升沿的30%
- Data Valid Time: 下一数据变稳定 SCL下升沿的30%
- Buffer time
https://www.analog.com/en/technical-articles/i2c-timing-definition-and-specification-guide-part-2.html
IIC下降沿快上升沿慢
https://blog.csdn.net/u010783226/article/details/127323258
上拉电阻计算
IIC信号测试方法
https://blog.csdn.net/weixin_43381663/article/details/131876767