预览
W7500P
IOP4IoT W7500P芯片是集成了ARM Cortex-M0、128KB Flash、用于各种嵌入式应用平台的硬件TCP/IP内核、10/100以太网MAC和PHY,尤其是物联网的单芯片解决方案。 TCP/IP 核心是经过市场验证的硬件 TCP/IP 堆栈,而 PHY 是 IC plus IP101G,这是一种用于 10/100Mbps 的 IEEE 802.3/802.3u 快速以太网收发器。 硬件 TCP/IP 堆栈支持 TCP、UDP、IPv4、ICMP、ARP、IGMP 和 PPPoE,已在各种应用中使用了 15 年以上。 W7500P 最适合需要 Internet 连接的用户。
特征
- ARM Cortex-M0
- 48MHz maximum frequency
- Hardwired TCP/IP Core
- 8 Sockets
- SRAM for socket: 32 KB
- PHY
- IC+(IP101G)
- Memories
- Flash: 128 KB
- SRAM: 16 KB
- ROM for boot code: 6 KB
- Clock, reset and supply management
- POR (Power-On Reset)
- Internal Voltage Regulator : 3.3V to 1.5V
- 8-to-24MHz external crystal oscillator
- Internal 8MHz RC Oscillator
- PLL for CPU clock
- ADC : 12bit, 8ch, 1Mbps
- DMA
- 6-channel DMA controller
- Peripheral supported: UARTs, SPIs
- GPIO
- 34 I/Os (15 IO x 2ea, 4 IO x 1ea)
- Debug mode
- Serial Wire Debug (SWD)
- Timer/PWM
- 1 Watchdog (32-bit down-counter)
- 4 Timers (32-bit or 16-bit down-counter)
- 8 PWMs (32-bit counter/timers with programmable 6-bit prescaler)
- Communication Interfaces
- 3 UART (2 UARTs with FIFO and Flow Control, 1 simple UART)
- 2 SPI
- 2 I2C (Master/Slave, Fast-mode (400 kbps))
- Crypto
- 1 RNG (Random Number Generator): 32-bit random number
- Package
- 64 TQFP (7x7 mm)
细节