uboot移植五：添加板级打印信息

一、初始化时钟

s5pv210内部的irom中有对时钟的初始化，但是其时钟配置不是三星官方的推荐的配置，它的配置是arm主频400MHz，在这里我们在lowlevel_init函数中重新初始化时钟，将主频初始化到1GHz。

初始化后时钟频率如下图所示：

时钟的初始化主要是向相关寄存器中写值，比较模式化，代码部分移植自三星官方，我主要在配置头文件include/configs/s5p_goni.h中添加相应的宏控制就行了， 这些宏主要控制时钟的MUX开关与DIV分频系数。

//clk
//#define CONFIG_CLK_667_166_166_133
//#define CONFIG_CLK_533_133_100_100
//#define CONFIG_CLK_800_200_166_133
//#define CONFIG_CLK_800_100_166_133
#define CONFIG_CLK_1000_200_166_133
//#define CONFIG_CLK_400_200_166_133
//#define CONFIG_CLK_400_100_166_133


#if defined(CONFIG_CLK_667_166_166_133)
#define APLL_MDIV       0xfa
#define APLL_PDIV       0x6
#define APLL_SDIV       0x1
#elif defined(CONFIG_CLK_533_133_100_100)
#define APLL_MDIV       0x215
#define APLL_PDIV       0x18
#define APLL_SDIV       0x1
#elif defined(CONFIG_CLK_800_200_166_133) || \
defined(CONFIG_CLK_800_100_166_133) || \
defined(CONFIG_CLK_400_200_166_133) || \
defined(CONFIG_CLK_400_100_166_133)
#define APLL_MDIV       0x64
#define APLL_PDIV       0x3
#define APLL_SDIV       0x1
#elif defined(CONFIG_CLK_1000_200_166_133)
#define APLL_MDIV       0x7d
#define APLL_PDIV       0x3
#define APLL_SDIV       0x1
#endif


#define APLL_LOCKTIME_VAL 0x2cf


#if defined(CONFIG_EVT1)
/* Set AFC value */
#define AFC_ON 0x00000000
#define AFC_OFF 0x10000010
#endif


#if defined(CONFIG_CLK_533_133_100_100)
#define MPLL_MDIV 0x190
#define MPLL_PDIV 0x6
#define MPLL_SDIV 0x2
#else
#define MPLL_MDIV 0x29b
#define MPLL_PDIV 0xc
#define MPLL_SDIV 0x1
#endif


#define EPLL_MDIV 0x60
#define EPLL_PDIV 0x6
#define EPLL_SDIV 0x2


#define VPLL_MDIV 0x6c
#define VPLL_PDIV 0x6
#define VPLL_SDIV 0x3


/* CLK_DIV0 */
#define APLL_RATIO 0
#define A2M_RATIO 4
#define HCLK_MSYS_RATIO 8
#define PCLK_MSYS_RATIO 12
#define HCLK_DSYS_RATIO 16
#define PCLK_DSYS_RATIO 20
#