uboot移植四：DDR初始化与代码重定位

最新推荐文章于 2023-10-24 14:56:13 发布

Wenlong_L

最新推荐文章于 2023-10-24 14:56:13 发布

阅读量2.7k

点赞数

分类专栏： uboot移植文章标签： uboot移植

本文链接：https://blog.csdn.net/Wenlong_L/article/details/80897837

版权

一、DDR初始化

在u-boot-2013.10\board\samsung\goni目录下新建mem_init.S文件，该文件被用来进行DDR的初始化。

1、修改Makefile与u-boot.lds链接脚本

在同目录的Makefile文件中的OTHER_OBJS变量后面添加mem_init.o，将mem_init.S文件加入到编译的目标文件之中，如下所示：

OTHER_OBJS := lowlevel_init.o mem_init.o

修改u-boot.lds文件的代码段，将mem_init.o链接到uboot靠前的位置。

.text :
{
*(.__image_copy_start)
CPUDIR/start.o (.text*)
board/samsung/goni/lowlevel_init.o (.text*)
board/samsung/goni/mem_init.o (.text*)
*(.text*)

}

2、DDR初始化代码

.globl mem_ctrl_asm_init
mem_ctrl_asm_init:

/* DMC0 Drive Strength (Setting 2X) */

ldr r0, =ELFIN_GPIO_BASE

ldr r1, =0x0000AAAA
str r1, [r0, #MP1_0DRV_SR_OFFSET]

ldr r1, =0x0000AAAA
str r1, [r0, #MP1_1DRV_SR_OFFSET]

ldr r1, =0x0000AAAA
str r1, [r0, #MP1_2DRV_SR_OFFSET]

ldr r1, =0x0000AAAA
str r1, [r0, #MP1_3DRV_SR_OFFSET]

ldr r1, =0x0000AAAA
str r1, [r0, #MP1_4DRV_SR_OFFSET]

ldr r1, =0x0000AAAA
str r1, [r0, #MP1_5DRV_SR_OFFSET]

ldr r1, =0x0000AAAA
str r1, [r0, #MP1_6DRV_SR_OFFSET]

ldr r1, =0x0000AAAA
str r1, [r0, #MP1_7DRV_SR_OFFSET]

ldr r1, =0x00002AAA
str r1, [r0, #MP1_8DRV_SR_OFFSET]

/* DMC1 Drive Strength (Setting 2X) */

ldr r0, =ELFIN_GPIO_BASE

ldr r1, =0x0000AAAA
str r1, [r0, #MP2_0DRV_SR_OFFSET]

ldr r1, =0x0000AAAA
str r1, [r0, #MP2_1DRV_SR_OFFSET]

ldr r1, =0x0000AAAA
str r1, [r0, #MP2_2DRV_SR_OFFSET]

ldr r1, =0x0000AAAA
str r1, [r0, #MP2_3DRV_SR_OFFSET]

ldr r1, =0x0000AAAA
str r1, [r0, #MP2_4DRV_SR_OFFSET]

ldr r1, =0x0000AAAA
str r1, [r0, #MP2_5DRV_SR_OFFSET]

ldr r1, =0x0000AAAA
str r1, [r0, #MP2_6DRV_SR_OFFSET]

ldr r1, =0x0000AAAA
str r1, [r0, #MP2_7DRV_SR_OFFSET]

ldr r1, =0x00002AAA
str r1, [r0, #MP2_8DRV_SR_OFFSET]

/* DMC0 initialization at single Type*/
ldr r0, =APB_DMC_0_BASE

ldr r1, =0x00101000 @PhyControl0 DLL parameter setting, manual 0x00101000
str r1, [r0, #DMC_PHYCONTROL0]

ldr r1, =0x00000086 @PhyControl1 DLL parameter setting, LPDDR/LPDDR2 Case
str r1, [r0, #DMC_PHYCONTROL1]

ldr r1, =0x00101002 @PhyControl0 DLL on
str r1, [r0, #DMC_PHYCONTROL0]

ldr r1, =0x00101003 @PhyControl0 DLL start
str r1, [r0, #DMC_PHYCONTROL0]

find_lock_val:
ldr r1, [r0, #DMC_PHYSTATUS] @Load Phystatus register value
and r2, r1, #0x7
cmp r2, #0x7 @Loop until DLL is locked
bne find_lock_val

and r1, #0x3fc0
mov r2, r1, LSL #18
orr r2, r2, #0x100000
orr r2 ,r2, #0x1000

orr r1, r2, #0x3 @Force Value locking
str r1, [r0, #DMC_PHYCONTROL0]

#if 0 /* Memory margin test 10.01.05 */
orr r1, r2, #0x1 @DLL off
str r1, [r0, #DMC_PHYCONTROL0]
#endif
/* setting DDR2 */
ldr r1, =0x0FFF2010 @ConControl auto refresh off
str r1, [