BASYS2开发板初学记录(4)——引脚约束

版权声明:本文为博主原创文章,未经博主允许不得转载。 https://blog.csdn.net/WilliamYuYuYu/article/details/78931625

BASYS2开发板初学记录(4)——引脚约束

2017-12-29

注:win10系统+软件Xilinx_ISE14.7+开发板BASYS2

关键词:

FPGA

BASYS2

Xilinx_ISE

Verilog

紧接着上篇,填第三个坑:引脚约束。


完整程序如下:

//管脚约束

NET "clk" TNM_NET = "clk";
TIMESPEC TS_clk = PERIOD "clk" 20 ns HIGH 50 %;


NET "clk" IOSTANDARD = LVCMOS25;


NET "clk" LOC = B8;

NET "ch1" LOC = B2;
NET "ch2" LOC = A3;
NET "ch3" LOC = J3;
NET "ch4" LOC = B5;
NET "ch5" LOC = A9;
NET "ch6" LOC = B9;

NET "ledout[3]" LOC = G1;
NET "ledout[2]" LOC = P4;
NET "ledout[1]" LOC = N4;
NET "ledout[0]" LOC = N5;

NET "pwmout1" LOC = C6;
NET "pwmout2" LOC = B6; 
NET "pwmout3" LOC = C5;
NET "pwmout4" LOC = B7;
NET "pwmout5" LOC = C12;


NET "clk" SLEW = FAST;

# PlanAhead Generated IO constraints 

关于写法:

其中 “LOC”代表管脚定义;

“IOSTANDARD”代表电平标准,可以设定为LVCMOS33;

“SLEW”代表信号的翻转速率,有fast和slow之分,默认是slow,时钟信号clk变化比较快可设定为fast。


最后,来一张图:
这里写图片描述

(2017-12-29–WilliamYu)

阅读更多

没有更多推荐了,返回首页