FPGA实战篇——【5】静态数码管

实验任务：六位数码管静态显示方式，每0.5s加1，从0-F显示

硬件设计

共阳极的6个数码管

此次使用静态显示，六个段选全部使能，六个显示相同的值。

程序设计

rtl文件

0.5s脉冲模块
module time_count(
	input      sys_clk,
	input      sys_rst_n,
	
	output reg flag            //在后面的always语句块中赋值，所以要用reg
	
	);
	
parameter  MAX_CNT = 25_000_000;

//0.5s计数器
reg [24:0]cnt;   // 0.5s/20ns = 25_000_000   只需要25位
	
always @(posedge sys_clk or negedge sys_rst_n)begin
	if(!sys_rst_n)begin
		cnt  <= 25'd0;
		flag <= 1'b0;
	end
	else if(cnt == MAX_CNT - 1'b1)begin
		cnt  <= 25'd0;
		flag <= 1'b1;
	end
	else begin
		cnt  <= cnt + 1'b1;
		flag <= 1'b0;         //这一句不能漏，否则只有第一次有效
	end	
end
	
/*	
always @(posedge sys_clk or negedge sys_rst_n)begin
	if(!sys_rst_n)begin
		cnt  <= 25'd0;
		flag <= 1'b0;
	end
	else if(cnt < MAX_CNT - 1'b1)begin
		cnt  <= cnt + 1'b1;
		flag <= 1'b0;
	end
	else begin
		cnt  <= 25'd0;  
		flag <= 1'b1;
	end	
end
*/
endmodule

静态数码管底层模块
module seg_led_static(
	input            sys_clk,
	input            sys_rst_n,
	
	input      		 add_flag,
	output reg [5:0] seg_sel,  //位选
	output reg [7:0] seg_dig   //段选
	
	);
	

reg [3:0] num;  //段选数字	
	
	
//首先实现位选
always @(posedge sys_clk or negedge sys_rst_n)begin
	if(!sys_rst_n)
		seg_sel  <= 6'b111111;  //共阳极，所以0为有效
	else 
		seg_sel  <= 6'b000000;
	
end

//实现段选
always @(posedge sys_clk or negedge sys_rst_n)begin
	if(!sys_rst_n)
		num       <= 4'h0;
	else if(add_flag) begin
		if(num == 4'hf)//加到了最大值F
			num   <= 4'h0;
		else 
			num   <= num + 1'b1;
	end
end

//翻译num
always @(posedge sys_clk or negedge sys_rst_n)begin
	if(!sys_rst_n)
		seg_dig <= 8'b0000_0000;
	else 
		case(num)			
			4'h0   : seg_dig <= 8'b1100_0000;
			4'h1   : seg_dig <= 8'b1111_1001;
			4'h2   : seg_dig <= 8'b1010_0100;
			4'h3   : seg_dig <= 8'b1011_0000;
			4'h4   : seg_dig <= 8'b1001_1001;
			4'h5   : seg_dig <= 8'b1001_0010;
			4'h6   : seg_dig <= 8'b1000_0010;
			4'h7   : seg_dig <= 8'b1111_1000;
			4'h8   : seg_dig <= 8'b1000_0000;
			4'h9   : seg_dig <= 8'b1001_0000;
			4'ha   : seg_dig <= 8'b1000_1000;
			4'hb   : seg_dig <= 8'b1000_0011;
			4'hc   : seg_dig <= 8'b1100_0110;
			4'hd   : seg_dig <= 8'b1010_0001;
			4'he   : seg_dig <= 8'b1000_0110;
			4'hf   : seg_dig <= 8'b1000_1110;
			default: seg_dig <= 8'b1100_0000;
		endcase
end
endmodule

顶层模块
module top_seg_led_static(
	input      sys_clk,
	input      sys_rst_n,
	
	output  [5:0] seg_sel,  //位选
	output  [7:0] seg_dig   //段选
	
	);
	
	
wire flag;

seg_led_static seg_led_static_u(
	.sys_clk(sys_clk),
	.sys_rst_n(sys_rst_n),
	
    .add_flag(flag),
    .seg_sel(seg_sel),  
    .seg_dig(seg_dig)  
	);
  
time_count time_count_u(
	.sys_clk  (sys_clk)  ,
	.sys_rst_n(sys_rst_n),
			  
	.flag     (flag)
	);
	
endmodule

ucf文件

NET sys_clk            TNM_NET = sys_clk_pin;
TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 20ns HIGH 50%;

NET sys_clk     LOC = T8 | IOSTANDARD = LVCMOS33;
NET sys_rst_n   LOC = L3 | IOSTANDARD = LVCMOS33;


##################################################################################
#seg pin define
################################################################################## 
NET seg_dig<0>             LOC = C7  | IOSTANDARD = "LVCMOS33"  | SLEW=FAST;
NET seg_dig<1>             LOC = E6  | IOSTANDARD = "LVCMOS33"  | SLEW=FAST; 
NET seg_dig<2>             LOC = C5  | IOSTANDARD = "LVCMOS33"  | SLEW=FAST;
NET seg_dig<3>             LOC = F7  | IOSTANDARD = "LVCMOS33"  | SLEW=FAST;
NET seg_dig<4>             LOC = D6  | IOSTANDARD = "LVCMOS33"  | SLEW=FAST;
NET seg_dig<5>             LOC = E7  | IOSTANDARD = "LVCMOS33"  | SLEW=FAST;
NET seg_dig<6>             LOC = D5  | IOSTANDARD = "LVCMOS33"  | SLEW=FAST;
NET seg_dig<7>             LOC = C6  | IOSTANDARD = "LVCMOS33"  | SLEW=FAST; 
NET seg_sel<0>             LOC = D9  | IOSTANDARD = "LVCMOS33"  | SLEW=FAST;
NET seg_sel<1>             LOC = E10 | IOSTANDARD = "LVCMOS33"  | SLEW=FAST;
NET seg_sel<2>             LOC = F10 | IOSTANDARD = "LVCMOS33"  | SLEW=FAST;
NET seg_sel<3>             LOC = F9  | IOSTANDARD = "LVCMOS33"  | SLEW=FAST;
NET seg_sel<4>             LOC = E8  | IOSTANDARD = "LVCMOS33"  | SLEW=FAST;
NET seg_sel<5>             LOC = D8  | IOSTANDARD = "LVCMOS33"  | SLEW=FAST; 

tb文件

`timescale 1ns / 1ps


module top_seg_led_static_tb;

	// Inputs
	reg sys_clk;
	reg sys_rst_n;

	// Outputs
	wire [5:0] seg_sel;
	wire [7:0] seg_dig;

	// Instantiate the Unit Under Test (UUT)
	top_seg_led_static u_top_seg_led_static (
		.sys_clk(sys_clk), 
		.sys_rst_n(sys_rst_n), 
		.seg_sel(seg_sel), 
		.seg_dig(seg_dig)
	);

	initial begin
		// Initialize Inputs
		sys_clk = 0;
		sys_rst_n = 0;

		// Wait 100 ns for global reset to finish
		#100;
        sys_rst_n = 1;
		// Add stimulus here

	end
      always #10 sys_clk = ~sys_clk;
endmodule

静态数码管这里没有什么太新的知识点，会用数码管（学过单片机的基本上都懂）怎么显示也没有太难的逻辑。下一篇再写动态显示。