冻结时间剩余!

import time
while True:
a=“2019-07-24 17:04:00” # 冻结时间
b=time.time()# 当前时间
e=7606024
c=time.mktime(time.strptime(“2019-07-24 17:04:00”,"%Y-%m-%d %H:%M:%S"))
d=c+e-b
day = d//(60
6024) #天
hour =d//(60
60)%24 #求小时
minute = d//60%60 # 分钟
seconds = d%60 # 秒
print("\r","%d天%d小时%d分%d秒"%(day,hour,minute,seconds),end="")
time.sleep(1)

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好的,我会尽力回答你的问题。针对你的问题,我给出如下的verilog代码。 ```verilog module stopwatch( input clk, input k0, input k1, output reg [3:0] seg, output reg [7:0] an ); reg [5:0] cnt; reg [31:0] time; reg [1:0] state; reg [2:0] debounce_k0; reg [2:0] debounce_k1; parameter IDLE = 2'b00; parameter RUN = 2'b01; parameter PAUSE = 2'b10; parameter FREEZE = 2'b11; // debounce k0 always @(posedge clk) begin debounce_k0 <= { debounce_k0[1:0], k0 }; end // debounce k1 always @(posedge clk) begin debounce_k1 <= { debounce_k1[1:0], k1 }; end // stopwatch state machine always @(posedge clk) begin case(state) IDLE: begin if(debounce_k0 == 3'b001) begin state <= RUN; end else begin time <= 0; cnt <= 0; seg <= 4'h0; an <= 8'b11111110; end end RUN: begin if(debounce_k0 == 3'b001) begin state <= PAUSE; end else begin time <= time + 1; if(cnt == 60) begin cnt <= 0; end else begin cnt <= cnt + 1; end end end PAUSE: begin if(debounce_k0 == 3'b001) begin state <= RUN; end else if(debounce_k1 == 3'b001) begin state <= FREEZE; end end FREEZE: begin if(debounce_k0 == 3'b001) begin state <= IDLE; end else if(debounce_k1 == 3'b001) begin time <= 0; cnt <= 0; seg <= 4'h0; an <= 8'b11111110; state <= IDLE; end end default: state <= IDLE; endcase end // display countdown time always @(posedge clk) begin if(state == RUN) begin if(cnt == 0) begin case(time) 0: begin seg <= 4'h0; an <= 8'b11111110; end 1: begin seg <= 4'h1; an <= 8'b11111101; end 2: begin seg <= 4'h2; an <= 8'b11111011; end 3: begin seg <= 4'h3; an <= 8'b11110111; end 4: begin seg <= 4'h4; an <= 8'b11101111; end 5: begin seg <= 4'h5; an <= 8'b11011111; end 6: begin seg <= 4'h6; an <= 8'b10111111; end 7: begin seg <= 4'h7; an <= 8'b01111111; end 8: begin seg <= 4'h8; an <= 8'b11111100; end 9: begin seg <= 4'h9; an <= 8'b11111000; end default: begin seg <= 4'h0; an <= 8'b11111110; end endcase end end end endmodule ``` 这是一个简单的秒表,可以实现你列出的基本功能。其中,使用7段数码管显示剩余时间。如果需要更多的解释,请随时询问!
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