如何instantiated?
module test;
parameter width = 8;
parameter reset_value = 0;
reg [width-1 : 0] data_in;
reg clk;
reg rst_n;
reg enable;
wire [width-1 : 0] data_out;
// Instance of DW03_reg_s_pl
DW03_reg_s_pl #(width, reset_value)
U1 ( .d(data_in), .clk(clk), .reset_N(rst_n),
.enable(enable), .q(data_out) );
...
endmodule
DUT长这样:
module DW03_reg_s_pl
(d, clk, reset_N, enable, q);
parameter integer width = 8;
parameter integer reset_value = 0;
input [width-1:0] d;
input clk, reset_N, enable;
output [width-1:0] q;
...
endmodule