Main.C时钟设定

void Main(void)   

　　　　　　 时钟设定：400M 100M  50M    得到  1:4:8  进而需要得到 hdivn=2 ； pdivn=1；

   i = 2 ;    //用于选择CUP核的频率；以及对应MPLL_vall ;key 参数；

  switch ( i )

        case 2: //400
                  key = 14;                                    key=14 指  hdivn_val (FCLK:HCLK) 1:4 ； hdivn=2
                  mpll_val = (92<<12)|(1<<4)|(1);   MPLL=2*(92+8)*12M/(1+2)*2^1=400M 
                  break;

//init FCLK=400M, so change MPLL first
 ChangeMPllValue((mpll_val>>12)&0xff, (mpll_val>>4)&0x3f, mpll_val&3);三个参数传递给rMPLLCON
 ChangeClockDivider(key, 12);                         12   指    (HCLK:PCLK)  1:2   ； pdivn=1
 cal_cpu_bus_clk();             400M 100M  50M    得到  1:4:8  进而得到 hdivn=2 ； pdivn=1；计算过程

1 //*************************[ MPLL ]*******************************
2 void ChangeMPllValue(int mdiv,int pdiv,int sdiv)
3 {
4     rMPLLCON = (mdiv<<12) | (pdiv<<4) | sdiv; //根据频率需求推算各个参数，传递给rMPLLCON，总分总的程序模式
5 }

 1 // Modified for 2440.
 2 void ChangeClockDivider(int hdivn_val,int pdivn_val)
 3 {
 4     int hdivn=2, pdivn=0;
 5     
 6      // hdivn_val (FCLK:HCLK)ratio hdivn
 7      // 11           1:1       (0)
 8      // 12           1:2       (1)
 9      // 13           1:3       (3) 
10      // 14           1:4       (2)
11      // pdivn_val (HCLK:PCLK)ratio pdivn
12      // 11           1:1       (0)
13      // 12           1:2       (1)
14     switch(hdivn_val) {
15         case 11: hdivn=0; break;
16         case 12: hdivn=1; break;
17         case 13:
18         case 16: hdivn=3; break;
19         case 14: 
20         case 18: hdivn=2; break;
21     }
22     
23     switch(pdivn_val) {
24         case 11: pdivn=0; break;
25         case 12: pdivn=1; break;
26     }
27     
28     //Uart_Printf("Clock division change [hdiv:%x, pdiv:%x]\n", hdivn, pdivn);
29     rCLKDIVN = (hdivn<<1) | pdivn;
30 
31     switch(hdivn_val) {    分频时钟在1:6或者1:8时，也会对摄像头时钟构成影响
32         case 16:        // when 1, HCLK=FCLK/8.
33             rCAMDIVN = (rCAMDIVN & ~(3<<8)) | (1<<8); 
34         break; 
35         case 18:     // when 1, HCLK=FCLK/6.
36             rCAMDIVN = (rCAMDIVN & ~(3<<8)) | (1<<9); 
37         break;
38     }
39     
40     if(hdivn!=0)            
41         MMU_SetAsyncBusMode();
42     else 
43         MMU_SetFastBusMode();
44 }

 1 static void cal_cpu_bus_clk(void)
 2 {
 3     U32 val;
 4     U8 m, p, s;
 5     
 6     val = rMPLLCON;
 7     m = (val>>12)&0xff;
 8     p = (val>>4)&0x3f;
 9     s = val&3;
10 
11     //(m+8)*FIN*2 不要超出32位数!
12     FCLK = ((m+8)*(FIN/100)*2)/((p+2)*(1<<s))*100;
13     
14     val = rCLKDIVN;
15     m = (val>>1)&3;
16     p = val&1;    
17     val = rCAMDIVN;
18     s = val>>8;
19     
20     switch (m) {
21     case 0:
22         HCLK = FCLK;
23         break;
24     case 1:
25         HCLK = FCLK>>1;
26         break;
27     case 2:
28         if(s&2)
29             HCLK = FCLK>>3;
30         else
31             HCLK = FCLK>>2;
32         break;
33     case 3:
34         if(s&1)
35             HCLK = FCLK/6;
36         else
37             HCLK = FCLK/3;
38         break;
39     }
40     
41     if(p)
42         PCLK = HCLK>>1;
43     else
44         PCLK = HCLK;
45     
46     if(s&0x10)
47         cpu_freq = HCLK;
48     else
49         cpu_freq = FCLK;
50         
51     val = rUPLLCON;
52     m = (val>>12)&0xff;
53     p = (val>>4)&0x3f;
54     s = val&3;
55     UPLL = ((m+8)*FIN)/((p+2)*(1<<s));
56     UCLK = (rCLKDIVN&8)?(UPLL>>1):UPLL;
57 }

 

转载于:https://www.cnblogs.com/wangh0802PositiveANDupward/p/3427773.html