9S12G48 时钟初始化

void CPMU_Init(void)
{
    /* ocs= 8  fbus =24*/
    /* 1: External oscillator is enabled */

    CPMUOSC_OSCE = 0x01u;
    /* 10: 6MHz<=fREF<=12MHz, 8M */
    CPMUREFDIV_REFFRQ = 0x10u;
    CPMUREFDIV_REFDIV = 0x00u;
    /* ICS Trim Register */
    CPMUIRCTRIM_IRCTRIM += 2u;
    /* 010111: fVCO=2*fREF*(SYNDIV+1) */
    CPMUSYNR_SYNDIV = 0x02u;
    /* 00: 32MHz<=fVCO<=48MHz */
    CPMUSYNR_VCOFRQ = 0x00u;
    /* 01: Enable PLL Frequency Modulation fVCO Variation = ±1% */
    CPMUPLL_FM = 0x01u;
    /* 00000: fPLL=fVCO/(POSTDIV+1) */
    CPMUPOSTDIV_POSTDIV = 0x00u; 
    /* 1: System clocks are derived from PLLCLK,fbus=fPLL/2 */
    CPMUCLKS_PLLSEL = 0x01u;
    while(!CPMUFLG_LOCK){}/* Wait for the PLL stabilization */
}

内部1m rc振荡器 初始化

void MCUex_init(void)
{

  /* ### MC9S12G64_64 "Cpu" init code ... */
  /*  PE initialization code after reset */
  /*  System clock initialization */
  /* CPMUPROT: PROT=0 */
  CPMUPROT = 0x26U;                    /* Disable protection of clock configuration registers */
  /* CPMUCLKS: PSTP=0 */
  CPMUCLKS &= (unsigned char)~(unsigned char)0x40U;                     
  /* CPMUCLKS: PLLSEL=1 */
  CPMUCLKS |= (unsigned char)0x80U;    /* Enable the PLL to allow write to divider registers */
  /* CPMUSYNR: VCOFRQ1=0,VCOFRQ0=1,SYNDIV5=0,SYNDIV4=1,SYNDIV3=1,SYNDIV2=1,SYNDIV1=1,SYNDIV0=1 */
  CPMUSYNR = 0x5FU;                    /* Set the multiplier register */
  /* CPMUPOSTDIV: POSTDIV4=0,POSTDIV3=0,POSTDIV2=0,POSTDIV1=1,POSTDIV0=1 */
  CPMUPOSTDIV = 0x03U;                 /* Set the post divider register */
  /* CPMUPLL: FM1=0,FM0=0 */
  CPMUPLL = 0x00U;                     /* Set the PLL frequency modulation */
  while(CPMUFLG_LOCK == 0U) {          /* Wait until the PLL is within the desired tolerance of the target frequency */
  }
  /* CPMUPROT: PROT=0 */
  CPMUPROT = 0x00U;                    /* Enable protection of clock configuration registers */
  /* CPMUCOP: RSBCK=0,WRTMASK=0 */
  CPMUCOP &= (unsigned char)~(unsigned char)0x60U;                     
  /* Common initialization of the CPU registers */
  /* CPMUINT: LOCKIE=0,OSCIE=0 */
  CPMUINT &= (unsigned char)~(unsigned char)0x12U;                     
  /* CPMULVCTL: LVIE=0 */
  CPMULVCTL &= (unsigned char)~(unsigned char)0x02U;                     
  /* IRQCR: IRQEN=0 */
  IRQCR &= (unsigned char)~(unsigned char)0x40U;                     
  /* ### */
  /* Initial interrupt priority */
  /*lint -save  -e950 Disable MISRA rule (1.1) checking. */
  //asm CLI;                             /* Enable interrupts */
  /*lint -restore Enable MISRA rule (1.1) checking. */
} /*MCU_init*/