比双周期简单,需要讲解和文件说明的可以评论并留邮箱,给发过去,这里只贴代码!
`timescale 1ns / 1ps
// Company:
// Engineer:
//
// Create Date: 17:51:43 03/30/2017
// Design Name: top
// Module Name: F:/mips_cpu/cpu_mips/top_tb.v
// Project Name: cpu_mips
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: top
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
module top_tb;
reg CLK;
reg RST;
top uut (
.CLK(CLK),
.RST(RST)
);
initial begin
// Initialize Inputs
CLK = 0;
RST = 0;
#5 RST=1;
#5 RST=0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
always #15 CLK=~CLK;
endmodule
`timescale 1ns / 1ps
//
// Company:
// Engineer:
//
// Create Date: 14:26:44 03/30/2017
// Design Name:
// Module Name: ALU
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//
module ALU(RST,inA,inB,out,ctr,ZF,OF,Over
);
input [31:0] inA,inB;
input [3:0] ctr;
input RST,Over;
output ZF,OF;
output [31:0] out;
wire [31:0] out;
wire ZF,OF,sign;
assign ZF=RST?1'b0:((out==32'd0)?1'b1:1'b0);
assign out=
(ctr==4'd0)?(inA+inB): //有符号加
(ctr==4'd1)?(inA-inB): //有符号减
(ctr==4'd2)?(inA&inB): //与
(ctr==4'd3)?(inA|inB): //或
(ctr==4'd4)?~(inA&inB): //与非
(ctr==4'd5)?~(inA|inB): //或非
(ctr==4'd6)?(inA^inB): //异或
(ctr==4'd7)?(inA<<inB): //逻辑左移
(ctr==4'd8)?(inA>>inB):inB; //逻辑右移
assign sign=out[31];
assign
OF=(
Over?(((ctr==4'd0)&&(inA[31]==0)&&(inB[31]==0)&&(sign==1))||
((ctr==4'd0)&&(inA[31]==1)&&(inB[31]==1)&&(sign==0))||
((ctr==4'd1)&&(inA[31]==1)&&(inB[31]==0)&&(sign==1))||
((ctr==4'd1)&&(inA[31]==0)&&(inB[31]==1)&&(sign==0))):0
);
endmodule
`timescale 1ns / 1ps
//
// Company:
// Engineer:
//
// Create Date: 17:02:31 03/16/