记录一次AC101音频codec芯片学习调试记录

AC101音频codec使用笔记

事情起因

手里有一块AC101 codec的音频开发板，由于未找到芯片相关技术手册，所以转而从esp-adf相关工程中提取芯片驱动及使用流程。

参考资料

1. 安信可所维护的esp-adf中ac101驱动文件
2. 基于esp-adf进行相关调试

1.初始化流程

esp_err_t ac101_init(audio_hal_codec_config_t *codec_cfg)
{

	//	if(i2c_init() < 0) return -1;

	//	esp_err_t res;

	esp_err_t res = ESP_OK;

	i2c_init(); // ESP32 in master mode

	res = ac101_write_reg(CHIP_AUDIO_RS, 0x123);
	vTaskDelay(1000 / portTICK_PERIOD_MS);

	ESP_LOGI(TAG, "ac101_init");

	if (res != ESP_OK)
	{
		ESP_LOGE(TAG, "reset failed!");
		return res;
	}
	else
	{
		ESP_LOGW(TAG, "reset succeed");
	}
	res |= ac101_write_reg(SPKOUT_CTRL, 0xe880);

	//Enable the PLL from 256*44.1KHz MCLK source
	res |= ac101_write_reg(PLL_CTRL1, 0x014f);
	//res |= ac101_write_reg(PLL_CTRL2, 0x83c0);
	res |= ac101_write_reg(PLL_CTRL2, 0x8600);

	//Clocking system
	res |= ac101_write_reg(SYSCLK_CTRL, 0x8b08);
	res |= ac101_write_reg(MOD_CLK_ENA, 0x800c);
	res |= ac101_write_reg(MOD_RST_CTRL, 0x800c);
	res |= ac101_write_reg(I2S_SR_CTRL, 0x7000); //sample rate
	//AIF config
	res |= ac101_write_reg(I2S1LCK_CTRL, 0x8850);	//BCLK/LRCK
	res |= ac101_write_reg(I2S1_SDOUT_CTRL, 0xc000); //
	res |= ac101_write_reg(I2S1_SDIN_CTRL, 0xc000);
	res |= ac101_write_reg(I2S1_MXR_SRC, 0x2200); //

	res |= ac101_write_reg(ADC_SRCBST_CTRL, 0xccc4);
	res |= ac101_write_reg(ADC_SRC, 0x2020);
	res |= ac101_write_reg(ADC_DIG_CTRL, 0x8000);
	res |= ac101_write_reg(ADC_APC_CTRL, 0xbbc3);

	//Path Configuration
	res |= ac101_write_reg(DAC_MXR_SRC, 0xcc00);
	res |= ac101_write_reg(DAC_DIG_CTRL, 0x8000);
	res |= ac101_write_reg(OMIXER_SR, 0x0081);
	res |= ac101_write_reg(OMIXER_DACA_CTRL, 0xf080); //}

	//* Enable Speaker output
	res |= ac101_write_reg(0x58, 0xeabd);

	ESP_LOGI(TAG, "init done");
	ac101_pa_power(true);
	return res;
}

2.相关接口调用流程

    行 68: I (2454) AC101: ac101_init
    行 68: I (2454) AC101: ac101_init
    行 69: W (2454) AC101: reset succeed
    行 70: I (2464) AC101: init done
    行 72: I (2464) AC101: ac101_pa_power enable:1
    行 72: I (2464) AC101: ac101_pa_power enable:1
    行 73: I (2464) AC101: ac101_config_i2s mode:3 bits:1 fmt:0 samples:7
    行 73: I (2464) AC101: ac101_config_i2s mode:3 bits:1 fmt:0 samples:7
    行 74: I (2474) AC101: ac101_set_voice_volume volume:70
    行 74: I (2474) AC101: ac101_set_voice_volume volume:70
    行 75: I (2474) AC101: ac101_set_earph_volume
    行 75: I (2474) AC101: ac101_set_earph_volume
    行 76: I (2484) AC101: ac101_set_spk_volume
    行 76: I (2484) AC101: ac101_set_spk_volume
    行 78: I (2494) AC101: ac101_ctrl_state mode:2 ctrl_state:1
    行 78: I (2494) AC101: ac101_ctrl_state mode:2 ctrl_state:1
    行 79: I (2494) AC101: AC101_start mode:2
    行 79: I (2494) AC101: AC101_start mode:2
    行 80: I (2614) AC101: ac101_set_voice_volume volume:30
    行 80: I (2614) AC101: ac101_set_voice_volume volume:30
    行 81: I (2614) AC101: ac101_set_earph_volume
    行 81: I (2614) AC101: ac101_set_earph_volume
    行 82: I (2614) AC101: ac101_set_spk_volume
    行 82: I (2614) AC101: ac101_set_spk_volume

3.完整参考代码

ac101.h

#ifndef __AC101_H__
#define __AC101_H__

//#include "sdkconfig.h"
#include "esp_types.h"
#include "audio_hal.h"

#define AC101_ADDR			0x1a				/*!< Device address*/

#define WRITE_BIT  			I2C_MASTER_WRITE 	/*!< I2C master write */
#define READ_BIT   			I2C_MASTER_READ  	/*!< I2C master read */
#define ACK_CHECK_EN   		0x1     			/*!< I2C master will check ack from slave*/
#define ACK_CHECK_DIS  		0x0     			/*!< I2C master will not check ack from slave */
#define ACK_VAL    			0x0         		/*!< I2C ack value */
#define NACK_VAL   			0x1         		/*!< I2C nack value */

#define CHIP_AUDIO_RS		0x00
#define PLL_CTRL1			0x01
#define PLL_CTRL2			0x02
#define SYSCLK_CTRL			0x03
#define MOD_CLK_ENA			0x04
#define MOD_RST_CTRL		0x05
#define I2S_SR_CTRL			0x06
#define I2S1LCK_CTRL		0x10
#define I2S1_SDOUT_CTRL		0x11
#define I2S1_SDIN_CTRL		0x12
#define I2S1_MXR_SRC		0x13
#define I2S1_VOL_CTRL1		0x14
#define I2S1_VOL_CTRL2		0x15
#define I2S1_VOL_CTRL3		0x16
#define I2S1_VOL_CTRL4		0x17
#define I2S1_MXR_GAIN		0x18
#define ADC_DIG_CTRL		0x40
#define ADC_VOL_CTRL		0x41
#define HMIC_CTRL1			0x44
#define HMIC_CTRL2			0x45
#define HMIC_STATUS			0x46
#define DAC_DIG_CTRL		0x48
#define DAC_VOL_CTRL		0x49
#define DAC_MXR_SRC			0x4c
#define DAC_MXR_GAIN		0x4d
#define ADC_APC_CTRL		0x50
#define ADC_SRC				0x51
#define ADC_SRCBST_CTRL		0x52
#define OMIXER_DACA_CTRL	0x53
#define OMIXER_SR			0x54
#define OMIXER_BST1_CTRL	0x55
#define HPOUT_CTRL			0x56
#define SPKOUT_CTRL			0x58
#define AC_DAC_DAPCTRL		0xa0
#define AC_DAC_DAPHHPFC 	0xa1
#define AC_DAC_DAPLHPFC 	0xa2
#define AC_DAC_DAPLHAVC 	0xa3
#define AC_DAC_DAPLLAVC 	0xa4
#define AC_DAC_DAPRHAVC 	0xa5
#define AC_DAC_DAPRLAVC 	0xa6
#define AC_DAC_DAPHGDEC 	0xa7
#define AC_DAC_DAPLGDEC 	0xa8
#define AC_DAC_DAPHGATC 	0xa9
#define AC_DAC_DAPLGATC 	0xaa
#define AC_DAC_DAPHETHD 	0xab
#define AC_DAC_DAPLETHD 	0xac
#define AC_DAC_DAPHGKPA 	0xad
#define AC_DAC_DAPLGKPA 	0xae
#define AC_DAC_DAPHGOPA 	0xaf
#define AC_DAC_DAPLGOPA 	0xb0
#define AC_DAC_DAPOPT   	0xb1
#define DAC_DAP_ENA     	0xb5

typedef enum{
	SAMPLE_RATE_8000	= 0x0000,
	SAMPLE_RATE_11052	= 0x1000,
	SAMPLE_RATE_12000	= 0x2000,
	SAMPLE_RATE_16000	= 0x3000,
	SAMPLE_RATE_22050	= 0x4000,
	SAMPLE_RATE_24000	= 0x5000,
	SAMPLE_RATE_32000	= 0x6000,
	SAMPLE_RATE_44100	= 0x7000,
	SAMPLE_RATE_48000	= 0x8000,
	SAMPLE_RATE_96000	= 0x9000,
	SAMPLE_RATE_192000	= 0xa000,
}ac_adda_fs_i2s1_t;

typedef enum{
	BCLK_DIV_1		= 0x0,
	BCLK_DIV_2		= 0x1,
	BCLK_DIV_4		= 0x2,
	BCLK_DIV_6		= 0x3,
	BCLK_DIV_8		= 0x4,
	BCLK_DIV_12		= 0x5,
	BCLK_DIV_16		= 0x6,
	BCLK_DIV_24		= 0x7,
	BCLK_DIV_32		= 0x8,
	BCLK_DIV_48		= 0x9,
	BCLK_DIV_64		= 0xa,
	BCLK_DIV_96		= 0xb,
	BCLK_DIV_128	= 0xc,
	BCLK_DIV_192	= 0xd,

}ac_i2s1_bclk_div_t;

typedef enum{
	LRCK_DIV_16		=0x0,
	LRCK_DIV_32		=0x1,
	LRCK_DIV_64		=0x2,
	LRCK_DIV_128	=0x3,
	LRCK_DIV_256	=0x4,
}ac_i2s1_lrck_div_t;

typedef enum {
    BIT_LENGTH_8_BITS = 0x00,
    BIT_LENGTH_16_BITS = 0x01,
    BIT_LENGTH_20_BITS = 0x02,
    BIT_LENGTH_24_BITS = 0x03,
} ac_bits_length_t;

typedef enum {
    AC_MODE_MIN = -1,
    AC_MODE_SLAVE = 0x00,
    AC_MODE_MASTER = 0x01,
    AC_MODE_MAX,
} ac_mode_sm_t;

typedef enum {
    AC_MODULE_MIN = -1,
    AC_MODULE_ADC = 0x01,
    AC_MODULE_DAC = 0x02,
    AC_MODULE_ADC_DAC = 0x03,
    AC_MODULE_LINE = 0x04,
    AC_MODULE_MAX
} ac_module_t;

typedef enum{
	SRC_MIC1	= 1,
	SRC_MIC2	= 2,
	SRC_LINEIN	= 3,
}ac_output_mixer_source_t;

typedef enum {
    GAIN_N45DB = 0,
    GAIN_N30DB = 1,
    GAIN_N15DB = 2,
    GAIN_0DB   = 3,
    GAIN_15DB  = 4,
    GAIN_30DB  = 5,
    GAIN_45DB  = 6,
    GAIN_60DB  = 7,
} ac_output_mixer_gain_t;

/**
 * @brief Configure AC101 clock
 */
typedef struct {
	ac_i2s1_bclk_div_t bclk_div;    /*!< bits clock divide */
	ac_i2s1_lrck_div_t lclk_div;    /*!< WS clock divide */
} ac_i2s_clock_t;


esp_err_t ac101_init(audio_hal_codec_config_t* codec_cfg);
esp_err_t ac101_deinit(void);
esp_err_t ac101_ctrl_state(audio_hal_codec_mode_t mode, audio_hal_ctrl_t ctrl_state);
esp_err_t ac101_config_i2s(audio_hal_codec_mode_t mode, audio_hal_codec_i2s_iface_t* iface);
esp_err_t ac101_set_voice_mute(bool enable);
esp_err_t ac101_set_voice_volume(int volume);
esp_err_t ac101_get_voice_volume(int* volume);
void ac101_pa_power(bool enable);

#endif

ac101.c

#include <string.h>
#include "driver/i2c.h"
#include "board.h"
#include "esp_log.h"
#include "ac101.h"

static char *TAG = "AC101";

static i2c_config_t ac_i2c_cfg = {
	.mode = I2C_MODE_MASTER,
	.sda_pullup_en = GPIO_PULLUP_ENABLE,
	.scl_pullup_en = GPIO_PULLUP_ENABLE,
	.master.clk_speed = 100000};

/*
 * operate function of codec
 */
audio_hal_func_t AUDIO_CODEC_AC101_CODEC_HANDLE = {
	.audio_codec_initialize = ac101_init,
	.audio_codec_deinitialize = ac101_deinit,
	.audio_codec_ctrl = ac101_ctrl_state,
	.audio_codec_config_iface = ac101_config_i2s,
	.audio_codec_set_mute = ac101_set_voice_mute,
	.audio_codec_set_volume = ac101_set_voice_volume,
	.audio_codec_get_volume = ac101_get_voice_volume,
};

#define AC_ASSERT(a, format, b, ...)          \
	if ((a) != 0)                             \
	{                                         \
		ESP_LOGE(TAG, format, ##__VA_ARGS__); \
		return b;                             \
	}

static esp_err_t ac101_write_reg(uint8_t reg_addr, uint16_t val)
{
	i2c_cmd_handle_t cmd = i2c_cmd_link_create();
	esp_err_t ret = 0;
	uint8_t send_buff[4];
	send_buff[0] = (AC101_ADDR << 1);
	send_buff[1] = reg_addr;
	send_buff[2] = (val >> 8) & 0xff;
	send_buff[3] = val & 0xff;
	ret |= i2c_master_start(cmd);
	ret |= i2c_master_write(cmd, send_buff, 4, ACK_CHECK_EN);
	ret |= i2c_master_stop(cmd);
	ret |= i2c_master_cmd_begin(I2C_NUM_0, cmd, 1000 / portTICK_RATE_MS);
	i2c_cmd_link_delete(cmd);
	return ret;
}

static esp_err_t i2c_example_master_read_slave(uint8_t DevAddr, uint8_t reg, uint8_t *data_rd, size_t size)
{
	if (size == 0)
	{
		return ESP_OK;
	}
	i2c_cmd_handle_t cmd = i2c_cmd_link_create();
	i2c_master_start(cmd);
	i2c_master_write_byte(cmd, (DevAddr << 1) | WRITE_BIT, ACK_CHECK_EN);
	i2c_master_write_byte(cmd, reg, ACK_CHECK_EN);
	i2c_master_start(cmd);
	i2c_master_write_byte(cmd, (DevAddr << 1) | READ_BIT, ACK_CHECK_EN); //check or not
	i2c_master_read(cmd, data_rd, size, ACK_VAL);
	i2c_master_stop(cmd);
	esp_err_t ret = i2c_master_cmd_begin(I2C_NUM_0, cmd, 1000 / portTICK_RATE_MS);
	i2c_cmd_link_delete(cmd);
	return ret;
}

static uint16_t ac101_read_reg(uint8_t reg_addr)
{
	uint16_t val = 0;
	uint8_t data_rd[2];
	i2c_example_master_read_slave(AC101_ADDR, reg_addr, data_rd, 2);
	val = (data_rd[0] << 8) + data_rd[1];
	return val;
}

static int i2c_init()
{
	int res = 0;
	get_i2c_pins(I2C_NUM_0, &ac_i2c_cfg);
	res |= i2c_param_config(I2C_NUM_0, &ac_i2c_cfg);
	res |= i2c_driver_install(I2C_NUM_0, ac_i2c_cfg.mode, 0, 0, 0);
	AC_ASSERT(res, "i2c_init error", -1);
	return res;
}

void set_codec_clk(audio_hal_iface_samples_t sampledata)
{
	uint16_t sample_fre;
	ESP_LOGI(TAG, "set_codec_clk:%d", sampledata);
	switch (sampledata)
	{
	case AUDIO_HAL_08K_SAMPLES:
		sample_fre = 8000;
		break;
	case AUDIO_HAL_11K_SAMPLES:
		sample_fre = 11025;
		break;
	case AUDIO_HAL_16K_SAMPLES:
		sample_fre = 16000;
		break;
	case AUDIO_HAL_22K_SAMPLES:
		sample_fre = 22050;
		break;
	case AUDIO_HAL_24K_SAMPLES:
		sample_fre = 24000;
		break;
	case AUDIO_HAL_32K_SAMPLES:
		sample_fre = 32000;
		break;
	case AUDIO_HAL_44K_SAMPLES:
		sample_fre = 44100;
		break;
	case AUDIO_HAL_48K_SAMPLES:
		sample_fre = 48000;
		break;
	default:
		sample_fre = 44100;
	}
	ac101_write_reg(I2S_SR_CTRL, sample_fre);
}

esp_err_t ac101_init(audio_hal_codec_config_t *codec_cfg)
{

	//	if(i2c_init() < 0) return -1;

	//	esp_err_t res;

	esp_err_t res = ESP_OK;

	i2c_init(); // ESP32 in master mode

	res = ac101_write_reg(CHIP_AUDIO_RS, 0x123);
	vTaskDelay(1000 / portTICK_PERIOD_MS);

	ESP_LOGI(TAG, "ac101_init");

	if (res != ESP_OK)
	{
		ESP_LOGE(TAG, "reset failed!");
		return res;
	}
	else
	{
		ESP_LOGW(TAG, "reset succeed");
	}
	res |= ac101_write_reg(SPKOUT_CTRL, 0xe880);

	//Enable the PLL from 256*44.1KHz MCLK source
	res |= ac101_write_reg(PLL_CTRL1, 0x014f);
	//res |= ac101_write_reg(PLL_CTRL2, 0x83c0);
	res |= ac101_write_reg(PLL_CTRL2, 0x8600);

	//Clocking system
	res |= ac101_write_reg(SYSCLK_CTRL, 0x8b08);
	res |= ac101_write_reg(MOD_CLK_ENA, 0x800c);
	res |= ac101_write_reg(MOD_RST_CTRL, 0x800c);
	res |= ac101_write_reg(I2S_SR_CTRL, 0x7000); //sample rate
	//AIF config
	res |= ac101_write_reg(I2S1LCK_CTRL, 0x8850);	//BCLK/LRCK
	res |= ac101_write_reg(I2S1_SDOUT_CTRL, 0xc000); //
	res |= ac101_write_reg(I2S1_SDIN_CTRL, 0xc000);
	res |= ac101_write_reg(I2S1_MXR_SRC, 0x2200); //

	res |= ac101_write_reg(ADC_SRCBST_CTRL, 0xccc4);
	res |= ac101_write_reg(ADC_SRC, 0x2020);
	res |= ac101_write_reg(ADC_DIG_CTRL, 0x8000);
	res |= ac101_write_reg(ADC_APC_CTRL, 0xbbc3);

	//Path Configuration
	res |= ac101_write_reg(DAC_MXR_SRC, 0xcc00);
	res |= ac101_write_reg(DAC_DIG_CTRL, 0x8000);
	res |= ac101_write_reg(OMIXER_SR, 0x0081);
	res |= ac101_write_reg(OMIXER_DACA_CTRL, 0xf080); //}

	//* Enable Speaker output
	res |= ac101_write_reg(0x58, 0xeabd);

	ESP_LOGI(TAG, "init done");
	ac101_pa_power(true);
	return res;
}

int ac101_get_spk_volume(void)
{
	int res;
	ESP_LOGI(TAG, "ac101_get_spk_volume");
	res = ac101_read_reg(SPKOUT_CTRL);
	res &= 0x1f;
	return res * 2;
}

esp_err_t ac101_set_spk_volume(uint8_t volume)
{
	if (volume > 0x3f)
		volume = 0x3f;
	volume = volume / 2;

	uint16_t res;
	esp_err_t ret;
	ESP_LOGI(TAG, "ac101_set_spk_volume");

	res = ac101_read_reg(SPKOUT_CTRL);
	res &= (~0x1f);
	volume &= 0x1f;
	res |= volume;
	ret = ac101_write_reg(SPKOUT_CTRL, res);
	return ret;
}

int ac101_get_earph_volume(void)
{
	int res;
	ESP_LOGI(TAG, "ac101_get_earph_volume");
	res = ac101_read_reg(HPOUT_CTRL);
	return (res >> 4) & 0x3f;
}

esp_err_t ac101_set_earph_volume(uint8_t volume)
{
	if (volume > 0x3f)
		volume = 0x3f;

	uint16_t res, tmp;
	esp_err_t ret;
	ESP_LOGI(TAG, "ac101_set_earph_volume");
	res = ac101_read_reg(HPOUT_CTRL);
	tmp = ~(0x3f << 4);
	res &= tmp;
	volume &= 0x3f;
	res |= (volume << 4);
	ret = ac101_write_reg(HPOUT_CTRL, res);
	return ret;
}

esp_err_t ac101_set_output_mixer_gain(ac_output_mixer_gain_t gain, ac_output_mixer_source_t source)
{
	uint16_t regval, temp, clrbit;
	esp_err_t ret;
	regval = ac101_read_reg(OMIXER_BST1_CTRL);
	ESP_LOGI(TAG, "ac101_set_output_mixer_gain");
	switch (source)
	{
	case SRC_MIC1:
		temp = (gain & 0x7) << 6;
		clrbit = ~(0x7 << 6);
		break;
	case SRC_MIC2:
		temp = (gain & 0x7) << 3;
		clrbit = ~(0x7 << 3);
		break;
	case SRC_LINEIN:
		temp = (gain & 0x7);
		clrbit = ~0x7;
		break;
	default:
		return -1;
	}
	regval &= clrbit;
	regval |= temp;
	ret = ac101_write_reg(OMIXER_BST1_CTRL, regval);
	return ret;
}

esp_err_t AC101_start(ac_module_t mode)
{

	ESP_LOGI(TAG, "AC101_start mode:%d", mode);

	esp_err_t res = 0;
	if (mode == AC_MODULE_LINE)
	{
		res |= ac101_write_reg(0x51, 0x0408);
		res |= ac101_write_reg(0x40, 0x8000);
		res |= ac101_write_reg(0x50, 0x3bc0);
	}
	if (mode == AC_MODULE_ADC || mode == AC_MODULE_ADC_DAC || mode == AC_MODULE_LINE)
	{
		//I2S1_SDOUT_CTRL
		//res |= ac101_write_reg(PLL_CTRL2, 0x8120);
		res |= ac101_write_reg(0x04, 0x800c);
		res |= ac101_write_reg(0x05, 0x800c);
		//res |= ac101_write_reg(0x06, 0x3000);
	}
	if (mode == AC_MODULE_DAC || mode == AC_MODULE_ADC_DAC || mode == AC_MODULE_LINE)
	{
		//* Enable Headphoe output
		res |= ac101_write_reg(OMIXER_DACA_CTRL, 0xff80);
		res |= ac101_write_reg(HPOUT_CTRL, 0xc3c1);
		res |= ac101_write_reg(HPOUT_CTRL, 0xcb00);
		vTaskDelay(100 / portTICK_PERIOD_MS);
		res |= ac101_write_reg(HPOUT_CTRL, 0xfbc0);

		//* Enable Speaker output
		res |= ac101_write_reg(SPKOUT_CTRL, 0xeabd);
		vTaskDelay(10 / portTICK_PERIOD_MS);
		ac101_set_voice_volume(30);
	}

	return res;
}

esp_err_t AC101_stop(ac_module_t mode)
{
	esp_err_t res = 0;
	ESP_LOGI(TAG, "AC101_stop mode:%d", mode);
	res |= ac101_write_reg(HPOUT_CTRL, 0x01);	//disable earphone
	res |= ac101_write_reg(SPKOUT_CTRL, 0xe880); //disable speaker
	return res;
}

esp_err_t ac101_deinit(void)
{
	ESP_LOGI(TAG, "AC101_deinit");
	return ac101_write_reg(CHIP_AUDIO_RS, 0x123); //soft reset
}

esp_err_t ac101_ctrl_state(audio_hal_codec_mode_t mode, audio_hal_ctrl_t ctrl_state)
{
	int res = 0;
	int es_mode_t = 0;

	ESP_LOGI(TAG, "ac101_ctrl_state mode:%d ctrl_state:%d", mode, ctrl_state);

	switch (mode)
	{
	case AUDIO_HAL_CODEC_MODE_ENCODE:
		es_mode_t = AC_MODULE_ADC;
		break;
	case AUDIO_HAL_CODEC_MODE_LINE_IN:
		es_mode_t = AC_MODULE_LINE;
		break;
	case AUDIO_HAL_CODEC_MODE_DECODE:
		es_mode_t = AC_MODULE_DAC;
		break;
	case AUDIO_HAL_CODEC_MODE_BOTH:
		es_mode_t = AC_MODULE_ADC_DAC;
		break;
	default:
		es_mode_t = AC_MODULE_DAC;
		ESP_LOGW(TAG, "Codec mode not support, default is decode mode");
		break;
	}
	if (AUDIO_HAL_CTRL_STOP == ctrl_state)
	{
		res = AC101_stop(es_mode_t);
	}
	else
	{
		res = AC101_start(es_mode_t);
	}
	return res;
}

esp_err_t ac101_config_i2s(audio_hal_codec_mode_t mode, audio_hal_codec_i2s_iface_t *iface)
{
	esp_err_t res = 0;
	int bits = 0;
	int fmat = 0;
	int sample_fre = 0;
	uint16_t regval;

	ESP_LOGI(TAG, "ac101_config_i2s mode:%d bits:%d fmt:%d samples:%d", mode, iface->bits, iface->fmt, iface->samples);

	switch (iface->bits) //0x10
	{
	// case AUDIO_HAL_BIT_LENGTH_8BITS:
	// 	bits = BIT_LENGTH_8_BITS;
	// 	break;
	case AUDIO_HAL_BIT_LENGTH_16BITS:
		bits = BIT_LENGTH_16_BITS;
		break;
	case AUDIO_HAL_BIT_LENGTH_24BITS:
		bits = BIT_LENGTH_24_BITS;
		break;
	default:
		bits = BIT_LENGTH_16_BITS;
	}

	switch (iface->fmt) //0x10
	{
	case AUDIO_HAL_I2S_NORMAL:
		fmat = 0x0;
		break;
	case AUDIO_HAL_I2S_LEFT:
		fmat = 0x01;
		break;
	case AUDIO_HAL_I2S_RIGHT:
		fmat = 0x02;
		break;
	case AUDIO_HAL_I2S_DSP:
		fmat = 0x03;
		break;
	default:
		fmat = 0x00;
		break;
	}

	switch (iface->samples)
	{
	case AUDIO_HAL_08K_SAMPLES:
		sample_fre = 8000;
		break;
	case AUDIO_HAL_11K_SAMPLES:
		sample_fre = 11025;
		break;
	case AUDIO_HAL_16K_SAMPLES:
		sample_fre = 16000;
		break;
	case AUDIO_HAL_22K_SAMPLES:
		sample_fre = 22050;
		break;
	case AUDIO_HAL_24K_SAMPLES:
		sample_fre = 24000;
		break;
	case AUDIO_HAL_32K_SAMPLES:
		sample_fre = 32000;
		break;
	case AUDIO_HAL_44K_SAMPLES:
		sample_fre = 44100;
		break;
	case AUDIO_HAL_48K_SAMPLES:
		sample_fre = 48000;
		break;
	default:
		sample_fre = 44100;
	}
	regval = ac101_read_reg(I2S1LCK_CTRL);
	regval &= 0xffc3;
	regval |= (iface->mode << 15);
	regval |= (bits << 4);
	regval |= (fmat << 2);
	res |= ac101_write_reg(I2S1LCK_CTRL, regval);
	res |= ac101_write_reg(I2S_SR_CTRL, sample_fre);
	return res;
}

esp_err_t AC101_i2s_config_clock(ac_i2s_clock_t *cfg)
{
	esp_err_t res = 0;
	uint16_t regval = 0;
	ESP_LOGI(TAG, "AC101_i2s_config_clock");

	regval = ac101_read_reg(I2S1LCK_CTRL);
	regval &= 0xe03f;
	regval |= (cfg->bclk_div << 9);
	regval |= (cfg->lclk_div << 6);
	res = ac101_write_reg(I2S1LCK_CTRL, regval);
	return res;
}

esp_err_t ac101_set_voice_mute(bool enable)
{
	esp_err_t res = 0;

	ESP_LOGI(TAG, "ac101_set_voice_mute enable:%d", enable);

	if (enable)
	{
		res = ac101_set_earph_volume(0);
		res |= ac101_set_spk_volume(0);
	}
	return res;
}

esp_err_t ac101_set_voice_volume(int volume)
{
	esp_err_t res;
	ESP_LOGI(TAG, "ac101_set_voice_volume volume:%d", volume);
	res = ac101_set_earph_volume(volume);
	res |= ac101_set_spk_volume(volume);
	return res;
}

esp_err_t ac101_get_voice_volume(int *volume)
{
	*volume = ac101_get_earph_volume();
	return 0;
}

void ac101_pa_power(bool enable)
{
	gpio_config_t io_conf;
	memset(&io_conf, 0, sizeof(io_conf));
	io_conf.intr_type = GPIO_PIN_INTR_DISABLE;
	io_conf.mode = GPIO_MODE_OUTPUT;
	io_conf.pin_bit_mask = BIT(PA_ENABLE_GPIO);
	io_conf.pull_down_en = 0;
	io_conf.pull_up_en = 0;
	gpio_config(&io_conf);

	ESP_LOGI(TAG, "ac101_pa_power enable:%d", enable);

	if (enable)
	{
		gpio_set_level(PA_ENABLE_GPIO, 1);
	}
	else
	{
		gpio_set_level(PA_ENABLE_GPIO, 0);
	}
}