HDLBits 刷题笔记
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Verilog HDL刷题网站HDLBits的个人学习笔记和答案。
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HDLBits(9)——Latches and Flip-Flops
HDLBits(9)——Latches and Flip-Flops----- 81. D flip-flop -----Problem StatementAnswer----- 82. D flip-flops -----Problem StatementAnswer1Answer2----- 83. DFF with reset -----Problem StatementAnswer----- 84. DFF with reset value -----Problem StatementAnswer-原创 2021-08-12 10:56:46 · 784 阅读 · 0 评论 -
HDLBits(8)——Karnaugh Map to Circuit
HDLBits(8)——Karnaugh Map to Circuit----- 73. 3-varible -----Problem StatementAnswer----- 74. 4-varible (a) -----Problem StatementAnswer----- 75. 4-varible (b) -----Problem StatementAnswer----- 76. 4-varible (c) -----Problem StatementAnswer----- 77. Minimum原创 2021-08-09 17:47:48 · 508 阅读 · 0 评论 -
HDLBits(7)——Multiplexer & Arithmetic Circuits
HDLBits(7)——Multiplexer & Arithmetic Circuits----- 61. 2-to-1 multiplexer -----Problem StatementAnswer----- 62. 2-to-1 bus multiplexer -----Problem StatementAnswer1----- 63. 9-to-1 multiplexer -----Problem StatementAnswer----- 64. 256-to-1 multiplexer原创 2021-08-04 23:20:09 · 240 阅读 · 0 评论 -
HDLBits(6)——Basic Gates
HDLBits(6)——Basic Gates----- 44. Wire -----Problem StatementAnswer----- 45. GND -----Problem StatementAnswer----- 46. NOR -----Problem StatementAnswer----- 47. Another gate -----Problem StatementAnswer----- 48. Two gates -----Problem StatementAnswer----- 4原创 2021-08-01 10:34:51 · 308 阅读 · 0 评论 -
HDLBits(5)——More Verilog Features
HDLBits(5)——More Verilog Features-----37. Conditional -----Problem StatementAnswerNote: Ternary conditional operator(三目运算符)-----38. Reduction -----Problem StatementAnswerNote: The reduction operators-----39. Gates100 -----Problem StatementAnswer-----40. Ve原创 2021-07-27 22:37:46 · 544 阅读 · 0 评论 -
HDLBits(4)——Procedures
HDLBits(4)——Procedures----- 29. Alwaysblock1 -----Problem StatementAnswerNoteNote: Always Block (Combinational)----- 30. Alwaysblock2 -----Problem StatementAnswerNote: Always Block (Clocked)Note: Blocking vs. Non-Blocking Assignment----- 31. Always if ----原创 2021-07-26 17:12:32 · 560 阅读 · 0 评论 -
HDLBits(3)——Modules
HDLBits(3)——Modules----- 20. Module -----Problem StatementAnswerNote: ModuleNote: Connecting Signals to Module Ports(模块实例化)----- 21. Module Pos -----Problem StatementAnswer----- 22. Module Name -----Problem StatementAnswer----- 23. Module Shift -----Proble原创 2021-07-25 21:51:41 · 478 阅读 · 0 评论 -
HDLBits(2)——Vectors
----- 11. Vector0 -----Problem StatementBuild a circuit that has one 3-bit input, then outputs the same vector, and also splits it into three separate 1-bit outputs. Connect output o0 to the input vector’s position 0, o1 to position 1, etc.In a diagram原创 2021-07-21 16:42:24 · 473 阅读 · 0 评论 -
HDLBits(1)——Getting Started & Basics
----- 1. Step One -----Problem StatementBuild a circuit with no inputs and one output. That output should always drive 1 (or logic high).Expected solution length: Around 1 line.Answermodule top_module( output one );// Insert your code here assig原创 2021-07-16 12:23:36 · 826 阅读 · 1 评论