HDLBits（1）——Getting Started & Basics

这些是本人在HDLBits上的实时学习记录，本专栏不定期更新。

----- 1. Step One -----

Problem Statement

Build a circuit with no inputs and one output. That output should always drive 1 (or logic high).

Expected solution length: Around 1 line.

Answer

module top_module( output one );

// Insert your code here
    assign one = 1;

endmodule

Warning

• Warning (13024): Output pins are stuck at VCC or GND

This warning says that an output pin never changes (is “stuck”). This can sometimes indicate a bug if the output pin shouldn’t be a constant. If this pin is not supposed to be constant, check for bugs that cause the value being assigned to never change (e.g., assign a = x & ~x;)

----- 2. Output Zero -----

Problem Statement

Build a circuit with no inputs and one output that outputs a constant 0.

Expected solution length: Around 1 line.

Answer

module top_module(
    output zero
);// Module body starts after semicolon

    assign zero = 0;

endmodule

Warning

• Warning (13024): Output pins are stuck at VCC or GND

----- 3. Wire -----

Problem Statement

Your task is to create a wire (in green) by adding an assign statement to connect in to out. The parts outside the box are not your concern, but you should know that your circuit is tested by connecting signals from our test harness to the ports on your top_module.

In addition to continuous assignments, Verilog has three other assignment types that are used in procedural blocks, two of which are synthesizable（可综合的）. We won’t be using them until we start using procedural blocks.

Expected solution length: Around 1 line.

Answer

module top_module( input in, output out );

    assign out = in;
    
endmodule

Note

• Wires are directional, so “assign in = out” is not equivalent.
• In a Verilog “continuous assignment” (assign left_side = right_side;), the value of the signal on the right side is driven onto the wire on the left side. The assignment is “continuous（持续的）” because the assignment continues all the time even if the right side’s value changes. A continuous assignment is not a one-time event（一次性事件）.

----- 4. Wire4 -----

Problem Statement

Create a module with 3 inputs and 4 outputs that behaves like wires that makes these connections:

• a -> w
• b -> x
• b -> y
• c -> z
  

The diagram below illustrates how each part of the circuit corresponds to each bit of Verilog code. From outside the module, there are three input ports and four output ports.

Answer

module top_module( 
    input a,b,c,
    output w,x,y,z );
    
    assign w = a;
	assign x = b;
	assign y = b;
	assign z = c;

endmodule

Note

• When you have multiple assign statements, the order in which they appear in the code does not matter.
• Input and output declarations actually declare a wire unless otherwise specified. Writing input wire a is the same as input a.（批注：input和output的声明默认声明为wire）
• The assign statements are not creating wires, they are creating the connections between the 7 wires that already exist.（批注：assign只是说明wire之间的关系，并不是创建wire）
• If we’re certain about the width of each signal, using the concatenation operator is equivalent and shorter: assign {w,x,y,z} = {a,b,b,c};

----- 5. Notgate -----

Problem Statement

Create a module that implements a NOT gate.

Use an assign statement. The assign statement will continuously (a change in the inputs immediately update the output) drive the inverse of in onto wire out.

Expected solution length: Around 1 line.

Answer

module top_module( input in, output out );

    assign out = ~in;
    
endmodule

----- 6. Andgate -----

Problem Statement

Create a module that implements an AND gate.

This circuit now has three wires (a, b, and out). Wires a and b already have values driven onto them by the input ports. But wire out currently is not driven by anything. Write an assign statement that drives out with the AND of signals a and b.

Expected solution length: Around 1 line.

Answer

module top_module( 
    input a, 
    input b, 
    output out );
    
    assign out = a & b;

endmodule

Note

• A wire (or “net”, as it’s more formally called) cannot have more than one driver, and a wire that has no drivers will have an undefined value (often treated as 0 when synthesizing hardware).（批注：一条wire有且只有一个驱动源，如果没有驱动源则在综合过程中看做逻辑0，这也意味着驱动源 “has a known value determined by something attached to it”）
• An assign statements will drive a logic level onto a wire.（批注：assign给予wire一个逻辑电平）

----- 7. Norgate -----

Problem Statement

Create a module that implements a NOR gate. A NOR gate is an OR gate with its output inverted. A NOR function needs two operators when written in Verilog.

Expected solution length: Around 1 line.

Answer

module top_module( 
    input a, 
    input b, 
    output out );
    
    assign out = ~(a | b);

endmodule

----- 8. Xnorgate -----

Problem Statement

Create a module that implements an XNOR gate.（批注：同或门/异或非门）

Expected solution length: Around 1 line.

Answer

module top_module( 
    input a, 
    input b, 
    output out );
    
    assign out = a ^~ b;
    // other way: assign out = ~(a ^ b);

endmodule

----- 9. Wire decl -----

Problem Statement

Create two intermediate wires (named anything you want) to connect the AND and OR gates together. Note that the wire that feeds the NOT gate is really wire out, so you do not necessarily need to declare a third wire here. Notice how wires are driven by exactly one source (output of a gate), but can feed multiple inputs.

If you’re following the circuit structure in the diagram, you should end up with four assign statements, as there are four signals that need a value assigned.

Expected solution length: Around 5 lines.

Answer

module top_module(
    input a,
    input b,
    input c,
    input d,
    output out,
    output out_n   ); 

	 wire ab, cd;
	 assign ab = a & b;
	 assign cd = c & d;
	 assign out = ab | cd;
	 assign out_n = ~out;

endmodule

----- 10. Chip 7458 -----

Problem Statement

Create a module with the same functionality as the 7458 chip. It has 10 inputs and 2 outputs. You may choose to use an assign statement to drive each of the output wires, or you may choose to declare (four) wires for use as intermediate signals, where each internal wire is driven by the output of one of the AND gates. For extra practice, try it both ways.

Expected solution length: Around 2–10 lines.

Answer1

module top_module ( 
    input p1a, p1b, p1c, p1d, p1e, p1f,
    output p1y,
    input p2a, p2b, p2c, p2d,
    output p2y );

	assign p1y = (p1a & p1b & p1c) | (p1d & p1e & p1f);
	assign p2y = (p2a & p2b) | (p2c & p2d);

endmodule

Answer2

module top_module ( 
    input p1a, p1b, p1c, p1d, p1e, p1f,
    output p1y,
    input p2a, p2b, p2c, p2d,
    output p2y );

    wire p11, p12, p21, p22;
	 
	assign p11 = p1a & p1b & p1c;
    assign p12 = p1d & p1e & p1f;
	assign p1y = p11 | p12;
	 
	assign p21 = p2a & p2b;
	assign p22 = p2c & p2d;
	assign p2y = p21 | p22;

endmodule