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原创 方舟の女:再论黑洞宇宙霍金熵,信息论,测不准原理和普朗克常数

<br />本按:<br />黄淼鑫,集智俱乐部的高人,是俺的活字典,读书之多估计可以和小平同志一拼,关键此人还随手就能写出长串的公式,这点事小平不能比拟的。<br />黄淼鑫大侠最近在总结有关信息论的分类(评述柴立和教授的文章《我们的世界真的存在吗?》),提到了一个神秘的人物,方舟の女。<br />方舟の女,那位大侠认识?<br /> <br />黄淼鑫按:<br />淼鑫赋值:方舟の女大约旅居或求学于北美,常在网络上狂掰“大爆炸”之类物理“玄学”,构思多有奇妙,且徜徉肆姿,落拓桀傲。以“

2010-06-12 16:09:00 3170

原创 信息论与算法复杂度

<br />曾经在2008年2月的MCM中发现了信息论在Sudoku游戏中的应用,发现了游戏过程中蕴含的熵这一本质,采用熵来衡量游戏的难度,最后根据熵减小的梯度方向来生成Sudoku游戏。<br />竟然发现在接下来的这两三年里,有若干研究者采用了我们这一思想。<br />曾经有一位西交大的学者谈了谈从信息论的角度来看算法复杂度。<br />还有一位北大的学生谈了谈排序算法中的信息熵和复杂度。<br />其实,我们可能都是独自发现了这一问题。<br /> <br />在这篇文章里,我们从信息论的角度证明

2010-06-12 16:02:00 1765 1

原创 链表学习--双向链表实现

<br />今天学习了链表的数据结构。他的主要思路为:<br />1. 他访问数据的方式不是数组的下标,而是他的节点的指针来访问。所以他可以更灵活的处理数据见得相关信息。不过他的速度肯定没有数组下标快的,空间也没有数组利用率高,可他的灵活性给了我们很大的方便。我们用链表的时候还是很多的。<br />2. 链表是用指针的指向来访问管理数据的,一个我们把数据存在一个节点里,一个节点包括:nData,节点的数据域,nNext,他指向的下一个指针,nPre他的上一个指针。如果他没有下一个指针或上

2010-06-04 22:06:00 561

原创 队列学习--数组实现

<br />今天学习了队列,队列的思路和栈差不多,他只是先进先出(FIFO)的方式。他的主要操作和栈有:IsEmpty判断空,EnQueue入队,(栈是push,不过没有什么大的区别)。DeQueue出队。其核心数据也是很相似,也有一个数据区域nData,不过他是队头nHand和队尾nTail。对头定位着将要出队的元素,队尾对应着入队的元素。<br />实现细节:也是为了能使操作简单一些,我们开始都从0开始,nTail指向的是入队时候数据要加的位置,也就是说他是先把该位置设置为入队的值,然后

2010-06-04 22:05:00 447

原创 栈学习---数组实现

<br />今天学习了栈,据说栈是一个很重要的数据结构。其主要的思想为:<br />1. 栈是一个后进先出的数据结构(last-in, first-out LIFO)。<br />2. 他的主要操作有“IsEmpty() 判断栈空。Push()插入数据。Pop弹出数据。<br />3. 他的核心数据为栈顶,栈数据区域。栈顶表示最后一个数据的位置,也表示了栈中数据的个数。我这里是有一个int来表示。栈空的时候,栈顶位置为0。要得到栈顶元素,只需要用nData[nTop]就可以了。nDa

2010-06-04 22:05:00 334

原创 合并排序

<br />这次我学的是合并排序。合并排序的主要思想是:把两个已经排序好的序列进行合并,成为一个排序好的<br />序列。例如:13579 2468这两个序列,各自都是排好序的,然后我们进行合并,成为123456789这样一个<br />排好序的序列。貌似这个跟排序关系不大,因为排序给的是一个乱的序列,而合并是合并的两个已经排序<br />好的序列。且慢,我们可以把需要排序的数据分解成N个子序列,当分解的子序列所包含数据个数为1的时<br />候,那么这个序列不久是有序了吗?然后

2010-06-04 21:59:00 1136 1

原创 希尔排序

<br />今天学习了希尔排序,他的主要思想借用了合并排序的思想。不过他不是左边一半右边一半,而是按照步长来分,随着步长减少,分成的组也越少。然后进行各组的插入排序。主要思路就是这样,我在百度百科的博客园找到了其相关学习资料,附上连接:<br />http://baike.baidu.com/view/178698.htm<br />http://www.cnblogs.com/nokiaguy/archive/2008/05/16/1199359.html<br />所以就不用写思路了哦,真笨,语文也

2010-06-04 21:57:00 396

原创 冒泡排序

<br />今天学习了冒泡排序,我开始还纳闷怎么书上没有冒泡排序!结果是我的看书不认真,给漏掉了,这次补上。呵呵。<br />冒泡排序的主要思路:<br />我们把要排序的数组A = {3,4,2,1} 看成一组水泡, <!--[endif]-->就像冒泡一样,轻的在上面,重的在下面,换成数据,就是小的在上面,大的在下面。 我们先把最轻的冒出到顶端,然后冒出第二轻的在最轻的下面,接着冒出第三轻的。依次内推。直到所有都冒出来了为止。<br />3.我们怎么做到把最轻的放在顶端呢?我们从最底下的

2010-06-04 21:56:00 519

原创 选择排序

<br />今天学习了选择排序,选择排序和冒泡排序思路上有一点相似,都是先确定最小元素,再确定第二笑元素,最后确定最大元素。他的主要流程如下:<br />1.加入一个数组A = {5,3,6,2,4,7},我们对他进行排序<br />2.确定最小的元素放在A[0]位置,我们怎么确定呢,首先默认最小元素为5,他的索引为0,然后用它跟3比较,比他打,则认为最小元素为3,他的索引为1,然后用3跟6比,发现比他小,最小元素还是3,然后跟2比,最小元素变成了2,索引为3,然后跟4比,跟7比。当比较结束之后

2010-06-04 21:56:00 372

原创 用堆实现优先队列

<br />昨天学习了用堆排序,今天学习了用堆实现优先队列。呵呵。都没有思路好记录的,记住堆的性质:<br />1.一个是他是一个数组(当然你也可以真的用链表来做。)。<br />2.他可以看做一个完全二叉树。注意是完全二叉树。所以他的叶子个数刚好是nSize / 2个。<br />3.我使用的下标从1开始,这样好算,如果节点的位置为i,他的父节点就是i/2,他的左孩子结点就是i*2,右孩子结点就是i*2+1,如果下标从0开始,要复杂一点。<br />4.他的父节点一定不比子节点

2010-06-04 21:55:00 423

原创 基数排序

<br />今天学了基数排序,据说他的时间复杂度也是O(n),他的思路就是:<br />没有计数排序那么理想,我们的数据都比较集中,都比较大,一般是4,5位。基本没有小的数据。<br />那我们的处理很简单,你不是没有小的数据嘛。我给一个基数,例如个位,个位都是[0-10)范围内的。先对他进行归类,把小的放上面,大的放下面,然后个位排好了,在来看10位,我们也这样把小的放上面,大的放下面,依次内推,直到最高位排好。那么不就排好了吗?我们只需要做d(基数个数)的循环就可以了。时间复杂度相当

2010-06-04 21:54:00 560

原创 计数排序

<br />计数排序,传说时间复杂度为0(n)的排序<br />计数排序:<br />今天学习了计数排序,貌似计数排序的复杂度为o(n)。很强大。他的基本思路为:<br />1.      我们希望能线性的时间复杂度排序,如果一个一个比较,显然是不实际的,书上也在决策树模型中论证了,比较排序的情况为nlogn的复杂度。<br />2.      既然不能一个一个比较,我们想到一个办法,就是如果我在排序的时候就知道他的位置,那不就是扫描一遍,把他放入他应该的位置不就可以了嘛。<br />3

2010-06-04 21:53:00 499

原创 插入排序

<br />今天我学习的是插入排序,插入排序主要思想是:把要排序的数字插入到已经排好的数据中。(我自己理<br />解的哈)。例如12356是已经排好的序,我们将4插入到他们中,时插入之后也是排好序的。这里显而易见<br />是插入到3的后面。变为123456.<br />实现思路:插入排序就是先是一个有序的数据,然后把要插入的数据插到指定的位置,而排序首先给的就<br />是无序的,我们怎么确定先得到一个有序的数据呢?答案就是:如果只有一个,当然是有序的咯。我们先<br />

2010-06-04 21:52:00 374

原创 快速排序学习4(最初版加随机版)

<br />这是最初版本的和随机版本的结合,我也修改了一下最初版本的小点东西,思路还是最初版的思路,只是我把分割符中的数据排好了而已。呵呵。。也没有什么号说的。奉上源代码:<br />#include <stdio.h>#include <stdlib.h>#include <time.h>//化分区间,找到最后元素的排序位置。并返回分隔的点(即最后一数据排序的位置)。//划分的区间是[nBegin, nEnd). pData是保存数据的指针int Partition(int* pD

2010-06-04 21:51:00 326

原创 快速排序学习3(最初版)

<br />这次学习了快速排序的最初版的思路,基本也一样,呵呵,不过他在分割的时候,是两边同时进行而已。注意一点就是他只是分割的大小,但是在分割处并不是排好的数据,所以要注意一下,不能去掉该数据的迭代。<br />直接奉上源代码:<br />#include <stdio.h>#include <stdlib.h>//化分区间,找到最后元素的排序位置。并返回分隔的点(即最后一数据排序的位置)。//划分的区间是[nBegin, nEnd). pData是保存数据的指针int Parti

2010-06-04 21:50:00 358

原创 快速排序学习2(随机化版本)

<br />学了快速排序的随机化版本,他和标准的版本没有什么质的区别,因为快速排序的最坏情况和平均情况效率差太远,所以用随机的版本来写一个更大概率平均的快速排序,也是书上的例子:<br />直接奉上源代码:<br />#include <stdio.h>#include <stdlib.h>#include <time.h>//化分区间,找到最后元素的排序位置。并返回分隔的点(即最后一数据排序的位置)。//划分的区间是[nBegin, nEnd). pData是保存数据的指针in

2010-06-04 21:49:00 339

原创 快速排序学习1

<br />快速排序学习:<br />今天我学习了快速排序,顾名思义,快速排序的速度是很快的,平均复杂度是nlogn,我也不知道是怎么算出来的,反正T(n) = 2T(n/2) + o(n) 这样怎么怎么推到就成了nLogn了,呵呵,有空去学习一下。希望会的人可以教我,我数学太烂了。废话少说,记录一下快速排序的思路:<br />1.分治的思想,把数组分成两份,两份分成4分,这样分到足够小,就能很好排序咯,然后把他们合起来,排序完成。<br />2.该分治思想和合并排序思想一样,但是处理上更搞

2010-06-04 21:47:00 404

原创 C++链表使用完整代码

<br />/* 练习使用链表:创建链表、遍历链表、查找节点、添加节点、删除节点*/#include "stdio.h"#include "string.h"#include "assert.h"#include "stdlib.h"#include "windows.h"#define COUNT 3//定义一个节点结构体struct NODE...{ unsigned long uID; char strName[16]; //用指

2010-06-04 18:38:00 896

原创 堆排序

本来还想写点思路的,词穷,不知道怎么组织,算了。只有贴源代码了。希望以后的我不要怪我哦!还可以看书嘛。书上讲的已经很清楚了哦。呵呵。由于是学习,所以只写了最大堆,也没有怎么优化和详细的测试。哎,无奈的贴上源代码:#include #include //交换两个整数。注意一定要if判断是否两个相等,如果//不相等才交换,如果相等也交换会出错的。a^a = 0inline void Swap(int& a, int& b){ if (a != b) {

2010-06-04 18:30:00 254

原创 数组循环移位

<br /><br />数组循环移位          <br />对于存有N个整数的数组,将其向左循环移动k个位置,(x0, x1,……, xn-1)变换为(xk, xk+1, …, xn-1, x0, x1, …, xk-1)<br />最直接的方法就是每次将首位的数放到一个临时的整型变量中,后面N-1个数一次左移,这样需要k次才能完成,而每次的复杂度是O(N),因此总共其复杂度是O(K * N)。<br /> while(k--) // 每次完成循环左移一位

2010-06-04 13:18:00 814

原创 排序算法总结

<br />花了很长时间终于把排序的基础学了一下,这段时间学了很多东西,总结一下:<br />学的排序算法有:插入排序,合并排序,冒泡排序,选择排序,希尔排序,堆排序,快速排序,计数排序,基数排序,桶排序(没有实现)。比较一下学习后的心得。<br />我不是很清楚他们的时间复杂度,也真的不知道他们到底谁快谁慢,因为书上的推导我确实只是小小了解,并没有消化。也没有完全理解他们的精髓,所以又什么错误的还需要高手指点。呵呵。<br />1.普及一下排序稳定,所谓排序稳定就是指:如果两个数相

2010-06-04 13:12:00 329

原创 两个数交换算法

<br />两个数交换算法(包含不用第3个变量而直接交换的情况)2006-12-17 20:07对两个数进行交换,在C中可采用指针实现,而在C++可使用引用来实现,无论是用指针还是引用,都要借助第3个变量。本文将介绍两种直接交换的算法<br />******************************* 后附有完整算法和测试程序<br />方法一:<br />采用整数的加(减)法实现,属于算术运算<br />void SwapWithAri( int & lhs, int & rhs

2010-06-04 13:09:00 1491

原创 深度优先搜索

深度优先搜索算法(Depth-First-Search),是搜索算法的一种。是沿着树的深度遍历树的节点,尽可能深的搜索树的分支。当节点v的所有边都己被探寻过,搜索将回溯到发现节点v的那条边的起始节点。这一过程一直进行到已发现从源节点可达的所有节点为止。如果还存在未被发现的节点,则选择其中一个作为源节点并重复以上过程,整个进程反复进行直到所有节点都被访问为止。属于盲目搜索。深度优先搜索是图论中的经典算法,利用深度优先搜索算法可以产生目标图的相应拓扑排序表,利用拓扑排序表可以方便的解

2010-06-03 23:47:00 477

ISSCC2021-T12-Brain-Computer Interfaces.pdf

Brain Computer Interfaces Fundamentals to Future Technologies

2021-03-23

ISSCC2021-T8.pdf

On-Chip Interconnects Basic Concepts, Designs, and Future Opportunities

2021-03-23

ISSCC2021-T7.pdf

Basic Design Approaches to Accelerating Deep Neural Networks

2021-03-23

ISSCC 2021 Tutorials Basics of DAC-based Wireline Transmitters

Basics of DAC-based Wireline Transmitters

2021-03-23

ISSCC 2021 Tutorials Calibration Techniques in ADCs

Calibration Techniques in ADCs

2021-03-23

ISSCC 2021 Tutorials Measuring and Evaluating the Security Level of Circuits

Measuring and Evaluating the Security Level of Circuits

2021-03-23

ISSCC 2021 Tutorials Silicon Photonics – from Basics to ASICs

Silicon Photonics – from Basics to ASICs

2021-03-23

ISSCC 2021 Tutorials Fundamentals of Memory Subsystem Design for HPC and AI

Fundamentals of Memory Subsystem Design for HPC and AI

2021-03-23

ISSCC 2020 Tutorials Fundamentals of RF and Mm-Wave Power Amplifier Designs

Fundamentals of RF and Mm-Wave Power Amplifier Designs

2021-03-23

ISSCC 2021 Short Course:Processor Clock Generation, Distribution

Processor Clock Generation, Distribution, and Clock SensorManagement Loops Phillip Restle, IBM

2021-03-23

ISSCC 2021 Short Course Clocking, Clock Distribution, and Clock Management

Clocking, Clock Distribution, and Clock Management in WirelineWireless Subsystems Mozhgan Mansuri, Intel

2021-03-23

ISSCC 2021 Short Course PLL Architectures, Tradeoffs, and Key Application

PLL Architectures, Tradeoffs, and Key Application Considerations Woogeun Rhee, Tsinghua University

2021-03-23

ISSCC 2021 Short Course PLLs, Clocking, and Clock Distribution

PLLs, Clocking, and Clock Distribution Introduction to PLLs Phase Noise, Modeling, and Key Wireless Design Considerations Behzad Razavi, UCLA

2021-03-23

Counterfeit Integrated Circuits

Integrated circuits (ICs) and other electronic components form the foundation of the modern systems and infrastructures responsible for energy, finance, communication, defense, and much more. Over the last decade or so, increasing globalization has resulted in a dramatic increase in vulnerabilities within the electronic component supply chain. In particular, the rise of counterfeit ICs has become one of the most serious issues faced by industry, government, and society. Counterfeit ICs are literally a multibillion dollar business and growing at an unprecedented rate, impacting the profits of intellectual property (IP) holders as well as their corporate identities and reputation. Due to the widespread use of electronic components in our day-to-day lives—both directly and indirectly—counterfeit components also pose substantial threats to the health, safety, and security of the population at large. This book is intended to serve as a resource for both beginners and experts in the counterfeit electronic components domain. For newcomers to the area, it shall introduce all of the necessary background material. This book aims to provide a comprehensive description of all different types of counterfeit ICs and the safety and security threat posed by these components. We believe a complete understanding of the detection of such components is a prerequisite if the community wants to stay ahead of the counterfeiters. The physical and electrical test methods described in this book provide guidance for the detection of these counterfeit components. We must also add design-for-anti-counterfeit (DFAC) measures into new ICs for a quick and easy counterfeit detection without the need to perform expensive physical and electrical test methods. This research-based book will provide the necessary road map for the government, industry, test labs, and academia throughout the world who are directly or indirectly impacted by this rampant attack of counterfeiting.

2018-12-20

VLSI-Design of Non-Volatile Memories

The electronics and information technology revolution continues, but it is a critical time in the development of technology. Once again, we stand on the brink of a new era where emerging research will yield exciting applications and products destined to transform and enrich our daily lives! The potential is staggering and the ultimate impact is unimaginable, considering the continuing marriage of technology with fields such as medicine, communications and entertainment, to name only a few. But who will actually be responsible for transforming these potential new products into reality? The answer, of course, is today’s (and tomorrow’s) design engineers! The design of integrated circuits today remains an essential discipline in support of technological progress, and the authors of this book have taken a giant step forward in the development of a practice-oriented treatise for design engineers who are interested in the practical, industry-driven world of integrated circuit design. The authors, Giovanni Campardo and Rino Micheloni, are very well qualified to effectively address this challenging objective. Both have a solid track record of leading design activities at the STMicroelectronics Flash Division. I should probably mention at this point my association with and knowledge of the accomplishments of these authors. In April 2003, they published a unique Special Issue on the subject of Flash Memories for the Proceedings of the IEEE, the journal for which I am Managing Editor. Therefore, I have firsthand knowledge of their approach to the development of very well crafted technical material.

2018-12-20

Emerging Memory Technologies Design Architecture and Applications

Emerging non-volatile memory (NVM) technologies, such as PCRAM and STT-RAM, are getting mature in recent years. These emerging NVM technologies have demonstrated great potentials to be the candidates for future computer memory architecture design. It is important for SoC designers and computer architects to understand the benefits and limitations of such emerging memory technologies, to improve the performance/power/reliability of future memory architectures. This chapter gives a brief introduction of these memory technologies, reviews recent advances in memory architecture design, discusses the benefits of using at various levels of memory hierarchy, and also reviews the mitigation techniques to overcome the limitations of applying such emerging memory technologies for future memory architecture design.

2018-12-20

Design Exploration of Emerging Nano-scale Non-volatile Memory

The analysis of big data at exascale (1018 bytes or flops) has introduced the emerging need to reexamine the existing hardware platform that can support intensive dataoriented computing. A big-data-driven application requires huge bandwidth with maintained low-power density. For example, web-searching application involves crawling, comparing, ranking, and paging of billions of web pages with extensive memory access. At the same time, the analysis of such a huge data at exascale is a national interest due to cybersecurity need. One needs to provide scalable bigdata storage and processing solution that can detect malicious attack from the sea of data, which is beyond the capability of a pure software-based data analytic solution. The key bottleneck is from the current data storage and processing hardware, which has not only the well-known memory wall and power wall with limited accessing bandwidth but also large leakage power at advanced CMOS technology nodes. One needs to design an energy-efficient hardware platform for future big-data storage that can also support data-intensive processing for data recognition in both image and security applications. Memory is any physical device that is able to temporarily or permanently hold the state of information. Memories can be generally classified into two categories: volatile and nonvolatile. Static and dynamic random-access memories (SRAM and DRAM) are examples of volatile memories that can be accessed in nanosecond of speed, but the stored data will be lost when powered off. The flash and hard disk drive (HDD) are examples of nonvolatile memories. Imagine the life where one can start a computer in the blink of an eye, without having to wait for the operation system to load, or transfer full-length high-definition movie by memory stick in seconds rather than hours. Such a life would happen if a universal nonvolatile memory could be developed that not only can retain information without external power but also can be accessed in high speed. In general, the following criteria examine the new memory technologies: (1) Scalability for high-density integration (2) Low energy consumption for mobile access (3) High endurance capable of 1012 writing/erasing cycles

2018-12-20

Advances in Memristors, Memristive Devices and Systems 忆阻器

The new Springer book, Advances in Memristors, Memristive Devices and Systems, consists of 20 contributed chapters by subject experts who are specialized in the various topics addressed in this book. The special chapters have been brought out in this book after a rigorous review process in the broad areas of modeling and applications of memristors, memristive devices and systems. Special importance was given to chapters offering practical solutions and novel methods for the recent research problems in the modeling and applications of memristors, memristive devices and systems. This book discusses trends and applications of memristors and memristive devices in engineering.

2018-12-20

Introduction to Magnetic Random-Access Memory

ASCONTEXTforthisbook,computermemoryhierarchyrangesfromcache(fastestandmostexpensive)tomainmemory,tomassstorage(slowestandleastexpensive).Cachememory,immediatelyaccessiblebythecentralprocessingunit,isusuallystaticrandom-accessmemory(SRAM).Mainmemoryisusuallydynamicrandom-accessmemory(DRAM);likeSRAM,itrequirespowertomaintainitsmemorystate,butadditionallymustbeelectricallyrefreshed,typicallyevery64ms(1).Massstorageisexemplifiedbynonvolatileflashmemory(oftheNANDandNORvarieties)andmagnetichard-diskdrives.

2018-12-20

ESD Protection in CMOS ICs

靜電放電(Electrostatic Discharge, ESD)是造成大多 數的電子元件或電子系統受到過度電性應力(Electrical Overstress EOS)破壞的主要因素。這種破壞會導致半導體 元件以及電腦系統等,形成一種永久性的毀壞,因而影響 積體電路(Integrated Circuits, ICs)的電路功能,而使 得電子產品工作不正常。 而靜電放電破壞的產生,多是由於人為因素所形成,但又很難避免。電子元件或系統在製造、生產、組裝、測試、存放、搬運等的過程中,靜電會累積在人體、儀器、儲放設備等之中,甚至在電子元件本身也會累積靜電,而人們在不知情的情況下,使這些物體相互接觸,因而形了一放電路徑,使得電子元件或系統遭到靜電放電的肆虐。

2018-12-20

VLSI-SoC From Algorithms to Circuits and System-on-Chip Design

This book contains extended and revised versions of the best papers that were presented during the 20th edition of the IFIP/IEEE WG10.5 International Conference on Very Large Scale Integration, a global System-on-a-Chip Design & CAD conference. The 20th conference was held at the Dream Inn Hotel, Santa Cruz, California, USA (October 7–10, 2012). Previous conferences have taken place in Edinburgh, Trondheim, Vancouver,Munich, Grenoble, Tokyo, Gramado, Lisbon, Montpellier, Darmstadt, Perth, Nice, Atlanta, Rhodes, Florian´opolis, Madrid, and Hong Kong.

2018-12-20

精通Visual C++6

精通Visual C++6精通Visual C++6精通Visual C++6精通Visual C++6

2010-04-13

高质量C++编程指南

高质量C++编程指南高质量C++编程指南高质量C++编程指南高质量C++编程指南

2010-04-13

Linux初学者入门

Linux初学者入门Linux初学者入门Linux初学者入门Linux初学者入门Linux初学者入门Linux初学者入门

2010-04-13

清华大学校园地图高清3D版本

清华大学校园地图高清3D版本.清华大学校园地图高清3D版本.清华大学校园地图高清3D版本.清华大学校园地图高清3D版本.

2010-04-13

很好用的图形布尔运算引擎

一个很好用的布尔运算库,支持与或非想减运算。封装的很好。支持多边形运算。

2010-04-13

Iterative methods for sparse linear systems (1st edition)

Iterative methods for sparse linear systems (1st edition)

2009-10-14

ZeniEDA熊猫EDA介绍

ZeniEDA熊猫EDA介绍 ZeniEDA熊猫EDA介绍ZeniEDA熊猫EDA介绍

2009-03-22

实时天气观测小软件(可以详细的知道各种外部天气条件哦)

实时天气观测小软件(可以详细的知道各种外部天气条件哦)

2009-02-27

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