数字电路之CPU设计一

@3-8译码器与指令译码器

3-8译码器与指令译码器

湖南大学数字电路CPU设计实验一GitHub

1、实验方法

采用基于FPGA进行数字逻辑电路设计的方法。
采用的软件工具是Quartus II。

2、实验步骤

1、新建，编写源代码。
(1).选择保存项和芯片类型：【File】-【new project wizard】-【next】（设置文件路径+设置project name为xor2）-【next】（设置文件名xor2.vhd—在【add】）-【properties】（type=AHDL）-【next】（family=FLEX10K；name=EPF10K10TI144-4）-【next】-【finish】
(2).新建：【file】-【new】（第二个AHDL File）-【OK】
2、写好源代码，保存文件（xor2.vhd）。
3、编译与调试。确定源代码文件为当前工程文件，点击【processing】-【start compilation】进行文件编译，编译成功。
4、波形仿真及验证。新建一个vector waveform file。按照程序所述插入a,b,c三个节点（a、b为输入节点，c为输出节点）。(操作为：右击 -【insert】-【insert node or bus】-【node finder】（pins=all；【list】）-【>>】-【ok】-【ok】)。任意设置a,b的输入波形…点击保存按钮保存。（操作为：点击name（如：A））-右击-【value】-【clock】（如设置period=200；offset=0），同理设置name B（如120，,60），保存）。然后【start simulation】，出name C的输出图。
5、时序仿真或功能仿真。
6、查看RTL Viewer:【Tools】-【netlist viewer】-【RTL viewer】。

3-8译码器

library lcdf_vhdl,ieee;
use ieee.std_logic_1164.all,lcdf_vhdl.func_prims.all;

entity zjw2018 is
port (A:in std_logic_vector(0 to 2);
      D:out std_logic_vector(0 to 7));
end zjw2018;

architecture structural of zjw2018 is

signal A0_n,A1_n,A2_n,and00_out,and01_out,and02_out,and03_out,and10_out,and11_out,
and12_out,and13_out,and14_out,and15_out,and16_out,and17_out:std_logic;

begin
inv_0:not1 port map(in1 => A(0),out1 => A0_n);
inv_1:not1 port map(A(1),A1_n);
inv_2:not1 port map(A(2),A2_n);

and_00:and_2 port map(A0_n,A1_n,and00_out);
and_01:and_2 port map(A(0),A1_n,and01_out);
and_02:and_2 port map(A0_n,A(1),and02_out);
and_03:and_2 port map(A(0),A(1),and03_out);

and_10:and_2 port map(and10_out,A2_n,D(0));
and_11:and_2 port map(and11_out,A2_n,D(1));
and_12:and_2 port map(and12_out,A2_n,D(2));
and_13:and_2 port map(and13_out,A2_n,D(3));
and_14:and_2 port map(and10_out,A(2),D(4));
and_15:and_2 port map(and11_out,A(2),D(5));
and_16:and_2 port map(and12_out,A(2),D(6));
and_17:and_2 port map(and13_out,A(2),D(7));

end structural;

指令译码器

library ieee;
use ieee.std_logic_1164.all;
entity zjw is
	port(EN:in std_logic;
	IR: in std_logic_vector(7 downto 0);
	order: out std_logic_vector(3 downto 0);
	RA,RB: out std_logic_vector(1 downto 0);
	MOVA,MOVB,MOVC,ADD,SUB,AND0,NOT0,SHR,SHL,JMP,JZ,JC,IN0,OUT0,NOP,HEAL: out std_logic);
end zjw;

architecture dec of zjw is
signal instruct: std_logic_vector(3 downto 0);
signal R1, R2: std_logic_vector(1 downto 0);
begin
	order <= instruct;
	RA <= R2;
	RB <= R1;
	instruct <= IR(7 downto 4);
	R1 <= IR(3 downto 2);
	R2 <= IR(1 downto 0);
	MOVA <= '1' when instruct & EN = "00111" and (R1 /= "11" and R2 /= "11") else '0';
	MOVB <= '1' when instruct & R1 & EN = "1111111" else '0';
	MOVC <= '1' when instruct & R2 & EN = "1111111" else '0';
	ADD <= '1' when instruct & EN = "10011" else '0';
	SUB <= '1' when instruct & EN = "01101" else '0';
	AND0 <= '1' when instruct & EN = "11101" else '0';
	NOT0 <= '1' when instruct & EN = "01011" else '0';
	SHR <= '1' when instruct & EN & R2= "1010100" else '0';
	SHL <= '1' when instruct & EN & R2= "1010111" else '0';
	JMP <= '1' when IR & EN = "000100001" else '0';
	JZ <= '1' when IR & EN = "000100011" else '0';
	JC <= '1' when IR & EN = "000100101" else '0';
	IN0 <= '1' when instruct & EN = "00101" else '0';
	OUT0 <= '1' when instruct & EN = "01001" else '0';
	NOP <= '1' when instruct & EN = "01111" else '0';
	HEAL <= '1' when instruct & EN = "10001" else '0';
end dec;

指令集