Xilinx ISE中的DCM的使用

Clocking Wizard - General Setup

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Use the General Setup dialog box to configure the Digital Clock Manager (DCM).

The primitive the Architecture Wizard will use to implement the DCM function depends on the FPGA device into which your design will be programmed:

• For Virtex-II, Virtex-II Pro and Spartan-3/3L devices, a DCM primitive will be used.

• For Spartan-3E/3A devices, a DCM_SP primitive will be used.   

For more information on DCM specifications and functional descriptions, refer to the product Data Sheets.

For more information on DCM usage and design considerations for your target device:

• Virtex-II^TM - Go to User Guides > Virtex-II > Virtex-II Platform FPGA User Guide > "Chapter 3: Design Considerations" > "Using Digital Clock Managers (DCMs)".

• Virtex-II Pro^TM - Go to User Guides > Virtex-II Pro > Virtex-II Pro and Virtex-II Pro X FPGA User Guide > "Chapter 3: Design Considerations" > "Digital Clock Manager (DCMs)".

Note When designing with a Virtex-II Pro device, the information in the XAPP685 Application Note should be considered whenever data is being transferred from rising to falling or falling to rising edge clocks. This includes applications where the DCM output is used to drive a DDR register and the clock is inverted using a local inversion.

• Spartan^TM-3/3L - Go to the XAPP462 Application Note.

DCM Ports

Each selectable pin has a corresponding checkbox to enable or disable the pin.

CLKIN

This pin is the clock input to the DCM. CLKIN is always enabled. CLKIN provides the source clock to the DCM. The frequency is specified in the Input Clock Frequency box. The source is specified in the CLKIN Source box.

CLKFB

This pin is the clock feedback input to the DCM. The selection in the Feedback Source box determines if CLKFB is enabled. A DCM requires a reference or feedback signal to provide delay-compensated output.

RST

This pin is the reset input to the DCM. RST is enabled when the checkbox is selected. If not enabled, RST will be tied to GND, and the DCM can only be reset upon configuration. For details about what occurs when RST is enabled, refer to the "Using Digital Clock Managers (DCM)" section in the "Design Considerations" chapter of the relevant FPGA User Guide (links provided above).

PSEN

This pin is the phase shift enable input to the DCM. PSEN is enabled when Phase Shift Type is set to Variable. When not enabled, PSEN is tied to GND.

To initiate variable phase shift operation, the PSEN input must be activated for one period of PSCLK. The phase change becomes effective after up to 100 CLKIN pulse cycles plus three PSCLK cycles, and is indicated by a High pulse on PSDONE. During the phase transition there are no sporadic changes or glitches on any output.

PSINCDEC

This pin is the phase shift increment/decrement input to the DCM. PSINCDEC is enabled when Phase Shift Type is set to Variable. When not enabled, PSINCDEC is tied to GND.

The PSINCDEC signal is synchronous to PSCLK and is used to increment or decrement the phase shift factor. To increment or decrement the phase shift, the PSINCDEC signal must be High for increment, or Low for decrement.

For Virtex-II, Virtex-II Pro and Spartan-3/3L devices, each increment or decrement will move the clock phase by 1/256 of clock period. For Spartan-3E and Spartan-3A devices, each increment or decrement will correspond to approximately 25 ps.

PSCLK

This pin is the phase shift clock input to the DCM. PSCLK is enabled when Phase Shift Type is set to Variable. When not enabled, PSCLK is tied to GND.

The PSCLK input can be sourced by the CLKIN signal to the DCM, or it can be a lower or higher frequency signal provided from any clock source (external or internal). The frequency range of PSCLK is defined by PSCLK_FREQ_LF / PSCLK_FREQ_HF. For more information, see the product Data Sheets.

CLK0 / CLK90 / CLK180 / CLK270

These output DCM pins provide coarse phase shifting. Each of these outputs is enabled when its checkbox is selected.

The CLK0, CLK90, CLK180, and CLK270 outputs are each phase shifted by 1/4 of the input clock period relative to each other.

Note CLK90 and CLK270 are not available in high-frequency mode.

CLKDV

This pin is the clock divide output of the DCM. CLKDV is enabled when the checkbox is selected.

The CLKDV output provides divided output clocks and the options are available in the Divide By Value list.

CLK2X / CLK2X180

The CLK2X and CLK2X180 output pins double the clock frequency. Each of these outputs is enabled when its checkbox is selected. CLK2X180 is the opposite phase of CLK2X.

Note CLK2X and CLK2X180 are not available in high-frequency mode.

CLKFX / CLKFX180

The CLKFX and CLKFX180 output pins provide fully digital, dedicated frequency synthesizer output to the DCM. Each of these outputs is enabled when its checkbox is selected. CLKFX180 is the opposite phase of CLKFX.

The output frequency is a function of the input clock frequency described by M and D, where M is the multiplier (numerator), and D is the divisor (denominator). M and D can be specified in the Clock Frequency Synthesizer dialog box. The Clock Frequency Synthesizer dialog box appears when CLKFX or CLKFX180 is enabled.

STATUS

The STATUS pin is an 8-bit output bus from the DCM. STATUS is enabled when the checkbox is selected.

Only bits 0 to 2 are defined. Bits 3 to 7 are connected to a floating signal; this signal is optimized during synthesis.

STATUS[0] indicates the overflow of the phase shift numerator and that the absolute delay range of the phase shift delay line is exceeded. STATUS[1] indicates the loss of the input clock, CLKIN, to the DCM. STATUS[2] indicates that CLKFX has stopped.

LOCKED

The LOCKED pin is an output to the DCM that activates after the DCM has achieved lock. LOCKED is enabled when the checkbox is selected.

To achieve lock, the DCM may need to sample several thousand clock cycles. After the DCM achieves lock, the LOCKED signal goes high. To guarantee that the system clock is established prior to the device waking up, the DCM can be set to delay the completion of the device. The STARTUP_WAIT attribute activates this feature. Until the LOCKED signal activates, the DCM output clocks are not valid and can exhibit glitches, spikes, or other spurious movement.

PSDONE

The PSDONE pin is the phase shift done output of the DCM. PSDONE is enabled when Phase Shift Type is set to Variable.

The PSDONE signal is synchronous to PSCLK and it indicates, by pulsing high for one period of PSCLK, that the requested phase shift was achieved. This signal also indicates that a new change to the phase shift numerator can be made. This output signal is not valid if the phase shift feature is not being used or is in FIXED mode.

Input Clock Frequency

The input clock frequency determines the value of the DLL_FREQUENCY_MODE and DFS_FREQUENCY_MODE attributes for the DCM. The Clocking Wizard accepts values that fall within the ranges specified in the product Data Sheets. The default selection is low frequency. When the DLL_FREQUENCY_MODE attribute is set to HIGH, the only outputs available from the DCM are CLK0, CLK180, CLKDV and LOCKED.

Note The Clocking Wizard checks that each output can operate in the valid range. To check the valid range for each individual output, see the product Data Sheets.

Note The DLL_FREQUENCY_MODE and DFS_FREQUENCY_MODE attributes do not apply to the Spartan-3E and Spartan-3A architectures. In these architectures, the DCM function uses a DCM_SP primitive instead of a DCM primitive.

The input clock frequency affects the CLKIN_PERIOD attribute. This attribute is always set by the Clocking Wizard, but is used by BitGen (the bitstream generation program) only when the CLKFX / CLKFX180 output is used. This attribute does not affect any timing constraints.

FREQUENCY IS DIVIDED BY 2

This text alerts you that the Divide Input Clock by 2 option is selected in the Advanced dialog box (accessed by clicking the Advanced button below).

CLKIN Source

CLKIN provides the source clock to the DCM.

External

The Clocking Wizard connects a dedicated input buffer (IBUFG or IBUFGDS) to the CLKIN input pin. The output of the IBUFG or IBUFGDS is also brought out as a port. This is done to give you the ability to connect the output of the IBUFG or IBUFGDS to other clock components. For example, when a DCM is used with RocketIO, the output immediately after the IBUFGDS is required as the input for the BREFCLK or BREFCLK2 pin of the RocketIO transceiver (when using the BREFCLK pins to input the reference clock).

The default selection for CLKIN Source is External.

Single

An IBUFG is instantiated in the module generated by the Clocking Wizard. This is the default selection when CLKIN Source is set to External.

Differential

An IBUFGDS is instantiated in the module generated by the Clocking Wizard.

For more detailed information about these buffers, see the Libraries Guides, available from the Software Manuals collection.

Internal

The Clocking Wizard connects the CLKIN input pin directly to the CLKIN pin on the DCM. The only components that can drive the CLKIN on the DCM are dedicated clock I/O, regular I/O, or clock buffers. When this DCM instantiation is placed into a design, you must connect the CLKIN pin to one of those components. Select Internal if you do not want an IBUFG to be inserted for CLKIN.

Divide By Value

The value selected is the clock division factor associated with the CLKDV output pin. This selection is available only when the CLKDV checkbox is selected.

Feedback Source

Specifies the feedback source to the CLKFB input of the DCM.

Note When either Internal or External is selected, a BUFG is connected to the DCM clock output used as the feedback (CLK0). This information is displayed in the table found in the Clock Buffers dialog box; click Next to access this dialog box. For any other connection, select Customize buffers in the Clock Buffers dialog box. You can also generate a board level clock by using a DDR register in the Clock Forwarding/Board Deskew flow.

External

The Clocking Wizard instantiates a global clock input buffer and connects it to CLKFB. The type of buffer is determined by the selection of Single or Differential.

Single

An IBUFG is instantiated in the module generated by the Clocking Wizard. This is the default selection when Feedback Source is set to External.

Differential

An IBUFGDS is instantiated in the module generated by the Clocking Wizard.

For more detailed information about these buffers, see the Libraries Guides, available from the Software Manuals collection.

Internal

The Clocking Wizard instantiates a global buffer (BUFG) and connects it as shown in the figure. The default selection for Feedback Source is Internal.

None

This is valid only when CLKFX or CLKFX180 output pin is used.

Feedback Value

Specifies the feedback value for the DCM.

1X

The CLK0 output provides the feedback clock.This is the default selection.

2X

The CLK2X output provides the feedback clock. This output is not available in high-frequency mode.

Note 2X is not available for Virtex-II Pro devices.

Use Duty Cycle Correction

This setting enables the 50/50 duty cycle for the 1X clock outputs CLK0, CLK90, CLK180 and CLK270.

Phase Shift

This controls the fine phase shifting capabilities of the DCM.

Note For Spartan-3 devices, phase shift is only supported in Low Frequency mode. If the Input Clock Frequency for a Spartan-3 device is set for High Frequency mode the Phase Shift selections are disabled, the phase shift Type is set to NONE, and the phase shift Value is set to 0. This applies to Spartan-3 devices; it does not apply to Spartan-3E and Spartan-3A devices.

Type

Determines whether fine phase shifting will be used and, if so, determines the type of phase shift employed.

NONE

This selection disables the phase shift feature.

FIXED

This selection enables the fine fixed phase shifting.

VARIABLE

This selection enables the variable fine phase shifting. When selected, PSEN, PSINCDEC, PSCLK, and PSDONE are enabled.

Value

This setting determines the amount of phase introduced by the DCM. The phase shift value is the numerator in the following equations:

Phase Shift (ns) = (Phase Shift Value/256) * PERIOD_clkin

Phase Shift (Degrees) = (Phase Shift Value/ 256) * 360

The full range of the phase shift value is always -255 to + 255, but its practical range varies with CLKIN frequency, as constrained by the FINE_SHIFT_RANGE attribute. For further details, see the product Data Sheets.

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